wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * board/config.h - configuration options, board specific |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H |
| 30 | |
| 31 | /* |
| 32 | * High Level Configuration Options |
| 33 | * (easy to change) |
| 34 | */ |
| 35 | |
| 36 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
| 38 | #define CONFIG_OCRTC 1 /* ...on a OCRTC board */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 39 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 41 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 42 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 43 | |
| 44 | #define CONFIG_BAUDRATE 9600 |
| 45 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
| 46 | |
| 47 | #undef CONFIG_BOOTARGS |
| 48 | #define CONFIG_BOOTCOMMAND "go fff00100" |
| 49 | |
| 50 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 51 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 52 | |
Ben Warren | 96e21f8 | 2008-10-27 23:50:15 -0700 | [diff] [blame] | 53 | #define CONFIG_PPC4xx_EMAC |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 54 | #define CONFIG_MII 1 /* MII PHY management */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 55 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 56 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
Ben Warren | 18cc7af | 2009-04-28 16:50:53 -0700 | [diff] [blame] | 57 | #define CONFIG_NET_MULTI |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 58 | |
Jon Loeliger | e18a106 | 2007-07-08 14:21:43 -0500 | [diff] [blame] | 59 | |
| 60 | /* |
Jon Loeliger | 659e2f6 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 61 | * BOOTP options |
| 62 | */ |
| 63 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 64 | #define CONFIG_BOOTP_BOOTPATH |
| 65 | #define CONFIG_BOOTP_GATEWAY |
| 66 | #define CONFIG_BOOTP_HOSTNAME |
| 67 | |
| 68 | |
| 69 | /* |
Jon Loeliger | e18a106 | 2007-07-08 14:21:43 -0500 | [diff] [blame] | 70 | * Command line configuration. |
| 71 | */ |
| 72 | #include <config_cmd_default.h> |
| 73 | |
| 74 | #define CONFIG_CMD_PCI |
| 75 | #define CONFIG_CMD_IRQ |
| 76 | #define CONFIG_CMD_ASKENV |
| 77 | #define CONFIG_CMD_ELF |
| 78 | #define CONFIG_CMD_BSP |
| 79 | #define CONFIG_CMD_EEPROM |
| 80 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 81 | |
| 82 | #define CONFIG_MAC_PARTITION |
| 83 | #define CONFIG_DOS_PARTITION |
| 84 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 85 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 86 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 87 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 88 | |
| 89 | /* |
| 90 | * Miscellaneous configurable options |
| 91 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 93 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
Jon Loeliger | e18a106 | 2007-07-08 14:21:43 -0500 | [diff] [blame] | 94 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 95 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 96 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 98 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 99 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 100 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 101 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 102 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 104 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 105 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 106 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 107 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | #define CONFIG_SYS_BASE_BAUD 691200 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 110 | |
| 111 | /* The following table includes the supported baudrates */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 112 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 113 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
| 114 | 57600, 115200, 230400, 460800, 921600 } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 115 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 116 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 117 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 118 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 120 | |
| 121 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
| 122 | |
| 123 | /*----------------------------------------------------------------------- |
| 124 | * PCI stuff |
| 125 | *----------------------------------------------------------------------- |
| 126 | */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 127 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
| 128 | #define PCI_HOST_FORCE 1 /* configure as pci host */ |
| 129 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 130 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 131 | #define CONFIG_PCI /* include pci support */ |
| 132 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
| 133 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 134 | /* resource configuration */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 135 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 136 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 137 | |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 138 | #define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ |
stroese | ad10dd9 | 2003-02-14 11:21:23 +0000 | [diff] [blame] | 139 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 140 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
| 141 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */ |
| 142 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ |
| 143 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ |
| 144 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ |
| 145 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| 146 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ |
| 147 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ |
| 148 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 149 | |
| 150 | /*----------------------------------------------------------------------- |
| 151 | * Start addresses for the final memory configuration |
| 152 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 154 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 155 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 156 | #define CONFIG_SYS_FLASH_BASE 0xFFFD0000 |
| 157 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 158 | #define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ |
| 159 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 160 | |
| 161 | /* |
| 162 | * For booting Linux, the board info and command line data |
| 163 | * have to be in the first 8 MB of memory, since this is |
| 164 | * the maximum mapped by the Linux kernel during initialization. |
| 165 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 166 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 167 | /*----------------------------------------------------------------------- |
| 168 | * FLASH organization |
| 169 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 170 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 171 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 172 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 174 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 175 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 176 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
| 177 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
| 178 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 179 | /* |
| 180 | * The following defines are added for buggy IOP480 byte interface. |
| 181 | * All other boards should use the standard values (CPCI405 etc.) |
| 182 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 183 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
| 184 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
| 185 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 186 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 188 | |
| 189 | #if 0 /* Use NVRAM for environment variables */ |
| 190 | /*----------------------------------------------------------------------- |
| 191 | * NVRAM organization |
| 192 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 9314cee | 2008-09-10 22:47:59 +0200 | [diff] [blame] | 193 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 194 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
| 195 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 196 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
| 197 | #define CONFIG_ENV_ADDR \ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 198 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ |
| 199 | #define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 200 | |
| 201 | #else /* Use EEPROM for environment variables */ |
| 202 | |
Jean-Christophe PLAGNIOL-VILLARD | bb1f8b4 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 203 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 204 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
| 205 | #define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 206 | /* total size of a CAT24WC08 is 1024 bytes */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 207 | #endif |
| 208 | |
| 209 | /*----------------------------------------------------------------------- |
| 210 | * I2C EEPROM (CAT24WC08) for environment |
| 211 | */ |
| 212 | #define CONFIG_HARD_I2C /* I2c with hardware support */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 214 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 215 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 216 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
| 217 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 218 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 219 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
| 220 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 221 | /* 16 byte page write mode using*/ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 222 | /* last 4 bits of the address */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 224 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 225 | /* |
| 226 | * Init Memory Controller: |
| 227 | * |
| 228 | * BR0/1 and OR0/1 (FLASH) |
| 229 | */ |
| 230 | |
| 231 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ |
| 232 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ |
| 233 | |
| 234 | /*----------------------------------------------------------------------- |
| 235 | * External Bus Controller (EBC) Setup |
| 236 | */ |
| 237 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 238 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 239 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
| 240 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 241 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 242 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 243 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
| 244 | #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 245 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 246 | /* Memory Bank 2 (PLD - FPGA-boot) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 247 | #define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 248 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 249 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 250 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 251 | /* Memory Bank 3 (PLD - OSL) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 252 | #define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 253 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 254 | #define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 255 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 256 | /* Memory Bank 4 (Spartan2 1) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 257 | #define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 258 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 259 | #define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 260 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 261 | /* Memory Bank 5 (Spartan2 2) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 262 | #define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 263 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 264 | #define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 265 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 266 | /* Memory Bank 6 (Virtex 1) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 267 | #define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 268 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 269 | #define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 270 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 271 | /* Memory Bank 7 (Virtex 2) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 272 | #define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 273 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 274 | #define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 275 | |
| 276 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 277 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 278 | |
| 279 | /*----------------------------------------------------------------------- |
| 280 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 281 | */ |
| 282 | |
| 283 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 284 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 285 | |
| 286 | /* On Chip Memory location */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 287 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
| 288 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 289 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 290 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
| 291 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ |
| 292 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| 293 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
| 294 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 295 | |
| 296 | |
| 297 | /* |
| 298 | * Internal Definitions |
| 299 | * |
| 300 | * Boot Flags |
| 301 | */ |
| 302 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 303 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 304 | |
| 305 | #endif /* __CONFIG_H */ |