blob: c645cef87650dbdf02182988bd22b689e5b0fd03 [file] [log] [blame]
wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2000
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * (C) Copyright 2004
6 * ARM Ltd.
7 * Philippe Robin, <philippe.robin@arm.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Andreas Engel48d01922008-09-08 14:30:53 +020028/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
wdenk3d3befa2004-03-14 15:06:13 +000029
30#include <common.h>
Stuart Wood8b616ed2008-06-02 16:42:19 -040031#include <watchdog.h>
wdenk3d3befa2004-03-14 15:06:13 +000032
Andreas Engel20c92262008-09-08 10:17:31 +020033#include "serial_pl01x.h"
wdenk3d3befa2004-03-14 15:06:13 +000034
35#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
36#define IO_READ(addr) (*(volatile unsigned int *)(addr))
37
Andreas Engel20c92262008-09-08 10:17:31 +020038/*
39 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
40 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
41 * Versatile PB has four UARTs.
42 */
wdenk3d3befa2004-03-14 15:06:13 +000043#define CONSOLE_PORT CONFIG_CONS_INDEX
44#define baudRate CONFIG_BAUDRATE
wdenk6705d812004-08-02 23:22:59 +000045static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
46#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
wdenk3d3befa2004-03-14 15:06:13 +000047
Andreas Engel20c92262008-09-08 10:17:31 +020048static void pl01x_putc (int portnum, char c);
49static int pl01x_getc (int portnum);
50static int pl01x_tstc (int portnum);
wdenk3d3befa2004-03-14 15:06:13 +000051
Andreas Engel48d01922008-09-08 14:30:53 +020052#ifdef CONFIG_PL010_SERIAL
wdenk3d3befa2004-03-14 15:06:13 +000053
54int serial_init (void)
55{
wdenk42dfe7a2004-03-14 22:25:36 +000056 unsigned int divisor;
wdenk3d3befa2004-03-14 15:06:13 +000057
wdenk42dfe7a2004-03-14 22:25:36 +000058 /*
59 ** First, disable everything.
60 */
61 IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0);
wdenk3d3befa2004-03-14 15:06:13 +000062
wdenk42dfe7a2004-03-14 22:25:36 +000063 /*
64 ** Set baud rate
65 **
66 */
67 switch (baudRate) {
68 case 9600:
69 divisor = UART_PL010_BAUD_9600;
70 break;
wdenk3d3befa2004-03-14 15:06:13 +000071
wdenk42dfe7a2004-03-14 22:25:36 +000072 case 19200:
73 divisor = UART_PL010_BAUD_9600;
74 break;
wdenk3d3befa2004-03-14 15:06:13 +000075
wdenk42dfe7a2004-03-14 22:25:36 +000076 case 38400:
77 divisor = UART_PL010_BAUD_38400;
78 break;
wdenk3d3befa2004-03-14 15:06:13 +000079
wdenk42dfe7a2004-03-14 22:25:36 +000080 case 57600:
81 divisor = UART_PL010_BAUD_57600;
82 break;
wdenk3d3befa2004-03-14 15:06:13 +000083
wdenk42dfe7a2004-03-14 22:25:36 +000084 case 115200:
85 divisor = UART_PL010_BAUD_115200;
86 break;
wdenk3d3befa2004-03-14 15:06:13 +000087
wdenk42dfe7a2004-03-14 22:25:36 +000088 default:
89 divisor = UART_PL010_BAUD_38400;
90 }
wdenk3d3befa2004-03-14 15:06:13 +000091
wdenk42dfe7a2004-03-14 22:25:36 +000092 IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM,
93 ((divisor & 0xf00) >> 8));
94 IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff));
wdenk3d3befa2004-03-14 15:06:13 +000095
wdenk42dfe7a2004-03-14 22:25:36 +000096 /*
97 ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
98 */
99 IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH,
100 (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN));
wdenk3d3befa2004-03-14 15:06:13 +0000101
wdenk42dfe7a2004-03-14 22:25:36 +0000102 /*
103 ** Finally, enable the UART
104 */
105 IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN));
106
Andreas Engel20c92262008-09-08 10:17:31 +0200107 return 0;
wdenk3d3befa2004-03-14 15:06:13 +0000108}
109
Andreas Engel48d01922008-09-08 14:30:53 +0200110#endif /* CONFIG_PL010_SERIAL */
Andreas Engel20c92262008-09-08 10:17:31 +0200111
Andreas Engel48d01922008-09-08 14:30:53 +0200112#ifdef CONFIG_PL011_SERIAL
Andreas Engel20c92262008-09-08 10:17:31 +0200113
114int serial_init (void)
115{
116 unsigned int temp;
117 unsigned int divider;
118 unsigned int remainder;
119 unsigned int fraction;
120
121 /*
122 ** First, disable everything.
123 */
124 IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0);
125
126 /*
127 ** Set baud rate
128 **
129 ** IBRD = UART_CLK / (16 * BAUD_RATE)
130 ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
131 */
132 temp = 16 * baudRate;
133 divider = CONFIG_PL011_CLOCK / temp;
134 remainder = CONFIG_PL011_CLOCK % temp;
135 temp = (8 * remainder) / baudRate;
136 fraction = (temp >> 1) + (temp & 1);
137
138 IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider);
139 IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction);
140
141 /*
142 ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
143 */
144 IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH,
145 (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
146
147 /*
148 ** Finally, enable the UART
149 */
150 IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR,
151 (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
152 UART_PL011_CR_RXE));
153
154 return 0;
155}
156
Andreas Engel48d01922008-09-08 14:30:53 +0200157#endif /* CONFIG_PL011_SERIAL */
Andreas Engel20c92262008-09-08 10:17:31 +0200158
wdenk42dfe7a2004-03-14 22:25:36 +0000159void serial_putc (const char c)
wdenk3d3befa2004-03-14 15:06:13 +0000160{
161 if (c == '\n')
Andreas Engel20c92262008-09-08 10:17:31 +0200162 pl01x_putc (CONSOLE_PORT, '\r');
wdenk3d3befa2004-03-14 15:06:13 +0000163
Andreas Engel20c92262008-09-08 10:17:31 +0200164 pl01x_putc (CONSOLE_PORT, c);
wdenk3d3befa2004-03-14 15:06:13 +0000165}
166
wdenk42dfe7a2004-03-14 22:25:36 +0000167void serial_puts (const char *s)
wdenk3d3befa2004-03-14 15:06:13 +0000168{
169 while (*s) {
170 serial_putc (*s++);
171 }
172}
173
wdenk42dfe7a2004-03-14 22:25:36 +0000174int serial_getc (void)
wdenk3d3befa2004-03-14 15:06:13 +0000175{
Andreas Engel20c92262008-09-08 10:17:31 +0200176 return pl01x_getc (CONSOLE_PORT);
wdenk3d3befa2004-03-14 15:06:13 +0000177}
178
wdenk42dfe7a2004-03-14 22:25:36 +0000179int serial_tstc (void)
wdenk3d3befa2004-03-14 15:06:13 +0000180{
Andreas Engel20c92262008-09-08 10:17:31 +0200181 return pl01x_tstc (CONSOLE_PORT);
wdenk3d3befa2004-03-14 15:06:13 +0000182}
183
wdenk42dfe7a2004-03-14 22:25:36 +0000184void serial_setbrg (void)
wdenk3d3befa2004-03-14 15:06:13 +0000185{
186}
187
Andreas Engel20c92262008-09-08 10:17:31 +0200188static void pl01x_putc (int portnum, char c)
wdenk3d3befa2004-03-14 15:06:13 +0000189{
wdenk42dfe7a2004-03-14 22:25:36 +0000190 /* Wait until there is space in the FIFO */
Stuart Wood8b616ed2008-06-02 16:42:19 -0400191 while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF)
192 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000193
194 /* Send the character */
195 IO_WRITE (port[portnum] + UART_PL01x_DR, c);
wdenk3d3befa2004-03-14 15:06:13 +0000196}
197
Andreas Engel20c92262008-09-08 10:17:31 +0200198static int pl01x_getc (int portnum)
wdenk3d3befa2004-03-14 15:06:13 +0000199{
wdenk42dfe7a2004-03-14 22:25:36 +0000200 unsigned int data;
wdenk3d3befa2004-03-14 15:06:13 +0000201
wdenk42dfe7a2004-03-14 22:25:36 +0000202 /* Wait until there is data in the FIFO */
Stuart Wood8b616ed2008-06-02 16:42:19 -0400203 while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE)
204 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000205
206 data = IO_READ (port[portnum] + UART_PL01x_DR);
207
208 /* Check for an error flag */
209 if (data & 0xFFFFFF00) {
210 /* Clear the error */
211 IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
212 return -1;
213 }
214
215 return (int) data;
wdenk3d3befa2004-03-14 15:06:13 +0000216}
217
Andreas Engel20c92262008-09-08 10:17:31 +0200218static int pl01x_tstc (int portnum)
wdenk3d3befa2004-03-14 15:06:13 +0000219{
Stuart Wood8b616ed2008-06-02 16:42:19 -0400220 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000221 return !(IO_READ (port[portnum] + UART_PL01x_FR) &
222 UART_PL01x_FR_RXFE);
wdenk3d3befa2004-03-14 15:06:13 +0000223}