blob: 375159e1ef6e3e19ce76a193743906139c637c59 [file] [log] [blame]
Vikas Manocha9fa32b12014-11-18 10:42:22 -08001/*
2 * (C) Copyright 2014
3 * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_STV0991_H
9#define __CONFIG_STV0991_H
Vikas Manocha9fa32b12014-11-18 10:42:22 -080010#define CONFIG_SYS_DCACHE_OFF
Vikas Manocha9fa32b12014-11-18 10:42:22 -080011#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
12#define CONFIG_BOARD_EARLY_INIT_F
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080013
Vikas Manocha9fa32b12014-11-18 10:42:22 -080014#define CONFIG_SYS_CORTEX_R4
15
Vikas Manocha9fa32b12014-11-18 10:42:22 -080016#define CONFIG_SYS_NO_FLASH
17
18/* ram memory-related information */
19#define CONFIG_NR_DRAM_BANKS 1
20#define PHYS_SDRAM_1 0x00000000
21#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
22#define PHYS_SDRAM_1_SIZE 0x00198000
23
24#define CONFIG_ENV_SIZE 0x10000
Vikas Manocha137d5b92015-07-02 18:29:37 -070025#define CONFIG_ENV_IS_IN_SPI_FLASH
26#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
27#define CONFIG_ENV_OFFSET 0x30000
Vikas Manocha9fa32b12014-11-18 10:42:22 -080028#define CONFIG_ENV_ADDR \
29 (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
30#define CONFIG_SYS_MAXARGS 16
31#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
32
33/* serial port (PL011) configuration */
Vikas Manocha9fa32b12014-11-18 10:42:22 -080034#define CONFIG_BAUDRATE 115200
Vikas Manocha39e47952014-12-01 12:27:54 -080035#define CONFIG_PL01X_SERIAL
Vikas Manocha9fa32b12014-11-18 10:42:22 -080036
37/* user interface */
Vikas Manochac55e7592014-11-18 10:42:24 -080038#define CONFIG_SYS_CBSIZE 1024
Vikas Manocha9fa32b12014-11-18 10:42:22 -080039#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
40 +sizeof(CONFIG_SYS_PROMPT) + 16)
41
42/* MISC */
43#define CONFIG_SYS_LOAD_ADDR 0x00000000
Vikas Manocha498b7c22014-12-01 12:27:53 -080044#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
Vikas Manocha9fa32b12014-11-18 10:42:22 -080045#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
46#define CONFIG_SYS_INIT_SP_OFFSET \
47 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Bin Menga1875592016-02-05 19:30:11 -080048/* U-Boot Load Address */
Vikas Manocha9fa32b12014-11-18 10:42:22 -080049#define CONFIG_SYS_TEXT_BASE 0x00010000
50#define CONFIG_SYS_INIT_SP_ADDR \
51 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
52
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080053/* GMAC related configs */
54
55#define CONFIG_MII
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080056#define CONFIG_DW_ALTDESCRIPTOR
57#define CONFIG_PHY_MICREL
58
59/* Command support defines */
60#define CONFIG_CMD_PING
61#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
62
Vikas Manochac55e7592014-11-18 10:42:24 -080063#define CONFIG_SYS_MEMTEST_START 0x0000
64#define CONFIG_SYS_MEMTEST_END 1024*1024
65#define CONFIG_CMD_MEMTEST
66
67/* Misc configuration */
68#define CONFIG_SYS_LONGHELP
69#define CONFIG_CMDLINE_EDITING
70
71#define CONFIG_BOOTDELAY 3
72#define CONFIG_BOOTCOMMAND "go 0x40040000"
Stefan Roesed126e012015-05-18 14:08:23 +020073
Vikas Manochae67abca2015-07-02 18:29:41 -070074/*
75+ * QSPI support
76+ */
77#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
Vikas Manochae67abca2015-07-02 18:29:41 -070078#define CONFIG_CQSPI_DECODER 0
79#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
80#define CONFIG_CMD_SPI
81
Vikas Manochae67abca2015-07-02 18:29:41 -070082#define CONFIG_CMD_SF
83#endif
84
Vikas Manocha9fa32b12014-11-18 10:42:22 -080085#endif /* __CONFIG_H */