| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Matt Waddel | b80e41a | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010 Linaro |
| 4 | * Matt Waddel, <matt.waddel@linaro.org> |
| Matt Waddel | b80e41a | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 5 | */ |
| 6 | #ifndef _SYSTIMER_H_ |
| 7 | #define _SYSTIMER_H_ |
| 8 | |
| 9 | /* AMBA timer register base address */ |
| 10 | #define SYSTIMER_BASE 0x10011000 |
| 11 | |
| 12 | #define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */ |
| 13 | #define SYSTIMER_RELOAD 0xFFFFFFFF |
| 14 | #define SYSTIMER_EN (1 << 7) |
| 15 | #define SYSTIMER_32BIT (1 << 1) |
| Rob Herring | 714d1f5 | 2013-06-12 22:24:49 -0500 | [diff] [blame] | 16 | #define SYSTIMER_PRESC_16 (1 << 2) |
| 17 | #define SYSTIMER_PRESC_256 (1 << 3) |
| Matt Waddel | b80e41a | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 18 | |
| 19 | struct systimer { |
| 20 | u32 timer0load; /* 0x00 */ |
| 21 | u32 timer0value; |
| 22 | u32 timer0control; |
| 23 | u32 timer0intclr; |
| 24 | u32 timer0ris; |
| 25 | u32 timer0mis; |
| 26 | u32 timer0bgload; |
| 27 | u32 timer1load; /* 0x20 */ |
| 28 | u32 timer1value; |
| 29 | u32 timer1control; |
| 30 | u32 timer1intclr; |
| 31 | u32 timer1ris; |
| 32 | u32 timer1mis; |
| 33 | u32 timer1bgload; |
| 34 | }; |
| 35 | #endif /* _SYSTIMER_H_ */ |