| Vipin KUMAR | a6e34f7 | 2010-01-15 19:15:45 +0530 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 |
| 3 | * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef SPR_SMI_H |
| 25 | #define SPR_SMI_H |
| 26 | |
| 27 | /* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ |
| 28 | /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ |
| 29 | |
| 30 | #define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE |
| 31 | #define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE |
| 32 | |
| 33 | #define SMIBANK0_BASE (FLASH_START_ADDRESS) |
| 34 | #define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) |
| 35 | #define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) |
| 36 | #define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) |
| 37 | |
| 38 | #define BANK0 0 |
| 39 | #define BANK1 1 |
| 40 | #define BANK2 2 |
| 41 | #define BANK3 3 |
| 42 | |
| 43 | struct smi_regs { |
| 44 | u32 smi_cr1; |
| 45 | u32 smi_cr2; |
| 46 | u32 smi_sr; |
| 47 | u32 smi_tr; |
| 48 | u32 smi_rr; |
| 49 | }; |
| 50 | |
| 51 | /* CONTROL REG 1 */ |
| 52 | #define BANK_EN 0x0000000F /* enables all banks */ |
| 53 | #define DSEL_TIME 0x00000060 /* Deselect time */ |
| 54 | #define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ |
| 55 | #define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ |
| 56 | #define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ |
| 57 | #define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ |
| 58 | #define SW_MODE 0x10000000 /* enables SW Mode */ |
| 59 | #define WB_MODE 0x20000000 /* Write Burst Mode */ |
| 60 | #define FAST_MODE 0x00008000 /* Fast Mode */ |
| 61 | #define HOLD1 0x00010000 |
| 62 | |
| 63 | /* CONTROL REG 2 */ |
| 64 | #define RD_STATUS_REG 0x00000400 /* reads status reg */ |
| 65 | #define WE 0x00000800 /* Write Enable */ |
| 66 | #define BANK0_SEL 0x00000000 /* Select Banck0 */ |
| 67 | #define BANK1_SEL 0x00001000 /* Select Banck1 */ |
| 68 | #define BANK2_SEL 0x00002000 /* Select Banck2 */ |
| 69 | #define BANK3_SEL 0x00003000 /* Select Banck3 */ |
| 70 | #define BANKSEL_SHIFT 12 |
| 71 | #define SEND 0x00000080 /* Send data */ |
| 72 | #define TX_LEN_1 0x00000001 /* data length = 1 byte */ |
| 73 | #define TX_LEN_2 0x00000002 /* data length = 2 byte */ |
| 74 | #define TX_LEN_3 0x00000003 /* data length = 3 byte */ |
| 75 | #define TX_LEN_4 0x00000004 /* data length = 4 byte */ |
| 76 | #define RX_LEN_1 0x00000010 /* data length = 1 byte */ |
| 77 | #define RX_LEN_2 0x00000020 /* data length = 2 byte */ |
| 78 | #define RX_LEN_3 0x00000030 /* data length = 3 byte */ |
| 79 | #define RX_LEN_4 0x00000040 /* data length = 4 byte */ |
| 80 | #define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ |
| 81 | #define WCIE 0x00000200 /* WCF Interrupt Enable */ |
| 82 | |
| 83 | /* STATUS_REG */ |
| 84 | #define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ |
| 85 | #define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ |
| 86 | #define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ |
| 87 | #define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ |
| 88 | #define RSR 0x00000005 /* Read Status regiser */ |
| 89 | #define TFF 0x00000100 /* Transfer Finished FLag */ |
| 90 | #define WCF 0x00000200 /* Transfer Finished FLag */ |
| 91 | #define ERF1 0x00000400 /* Error Flag 1 */ |
| 92 | #define ERF2 0x00000800 /* Error Flag 2 */ |
| 93 | #define WM0 0x00001000 /* WM Bank 0 */ |
| 94 | #define WM1 0x00002000 /* WM Bank 1 */ |
| 95 | #define WM2 0x00004000 /* WM Bank 2 */ |
| 96 | #define WM3 0x00008000 /* WM Bank 3 */ |
| 97 | #define WM_SHIFT 12 |
| 98 | |
| 99 | /* TR REG */ |
| 100 | #define READ_ID 0x0000009F /* Read Identification */ |
| 101 | #define BULK_ERASE 0x000000C7 /* BULK erase */ |
| 102 | #define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ |
| 103 | #define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ |
| 104 | |
| 105 | struct flash_dev { |
| 106 | u32 density; |
| 107 | ulong size; |
| 108 | ushort sector_count; |
| 109 | }; |
| 110 | |
| 111 | #define SFLASH_PAGE_SIZE 0x100 /* flash page size */ |
| 112 | #define XFER_FINISH_TOUT 2 /* xfer finish timeout */ |
| 113 | #define WMODE_TOUT 2 /* write enable timeout */ |
| 114 | |
| 115 | #endif |