wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * IXP PCI Init |
| 3 | * (C) Copyright 2004 eslab.whut.edu.cn |
| 4 | * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) |
| 5 | * |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
Michael Schwingen | 29161f4 | 2011-05-23 00:00:12 +0200 | [diff] [blame] | 9 | #ifndef _IXP425PCI_H |
| 10 | #define _IXP425PCI_H |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 11 | |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 12 | #define OK 0 |
| 13 | #define ERROR -1 |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 14 | |
Michael Schwingen | 29161f4 | 2011-05-23 00:00:12 +0200 | [diff] [blame] | 15 | struct pci_controller; |
| 16 | extern void pci_ixp_init(struct pci_controller *hose); |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 17 | |
| 18 | /* Mask definitions*/ |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 19 | #define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 20 | |
| 21 | #define PCI_NP_CBE_BESL (4) |
| 22 | #define PCI_NP_AD_FUNCSL (8) |
| 23 | |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 24 | /*Register addressing definitions for PCI controller configuration |
| 25 | and status registers*/ |
| 26 | |
| 27 | #define PCI_CSR_BASE (0xC0000000) |
| 28 | /* |
| 29 | #define PCI_NP_AD_OFFSET (0x00) |
| 30 | #define PCI_NP_CBE_OFFSET (0x04) |
| 31 | #define PCI_NP_WDATA_OFFSET (0x08) |
| 32 | #define PCI_NP_RDATA_OFFSET (0x0C) |
| 33 | #define PCI_CRP_OFFSET (0x10) |
| 34 | #define PCI_CRP_WDATA_OFFSET (0x14) |
| 35 | #define PCI_CRP_RDATA_OFFSET (0x18) |
| 36 | #define PCI_CSR_OFFSET (0x1C) |
| 37 | #define PCI_ISR_OFFSET (0x20) |
| 38 | #define PCI_INTEN_OFFSET (0x24) |
| 39 | #define PCI_DMACTRL_OFFSET (0x28) |
| 40 | #define PCI_AHBMEMBASE_OFFSET (0x2C) |
| 41 | #define PCI_AHBIOBASE_OFFSET (0x30) |
| 42 | #define PCI_PCIMEMBASE_OFFSET (0x34) |
| 43 | #define PCI_AHBDOORBELL_OFFSET (0x38) |
| 44 | #define PCI_PCIDOORBELL_OFFSET (0x3C) |
| 45 | #define PCI_ATPDMA0_AHBADDR (0x40) |
| 46 | #define PCI_ATPDMA0_PCIADDR (0x44) |
| 47 | #define PCI_ATPDMA0_LENADDR (0x48) |
| 48 | #define PCI_ATPDMA1_AHBADDR (0x4C) |
| 49 | #define PCI_ATPDMA1_PCIADDR (0x50) |
| 50 | #define PCI_ATPDMA1_LENADDR (0x54) |
| 51 | #define PCI_PTADMA0_AHBADDR (0x58) |
| 52 | #define PCI_PTADMA0_PCIADDR (0x5C) |
| 53 | #define PCI_PTADMA0_LENADDR (0x60) |
| 54 | #define PCI_PTADMA1_AHBADDR (0x64) |
| 55 | #define PCI_PTADMA1_PCIADDR (0x68) |
| 56 | #define PCI_PTADMA1_LENADDR (0x6C) |
| 57 | */ |
| 58 | /*Non prefetch registers bit definitions*/ |
| 59 | /* |
| 60 | #define NP_CMD_INTACK (0x0) |
| 61 | #define NP_CMD_SPECIAL (0x1) |
| 62 | #define NP_CMD_IOREAD (0x2) |
| 63 | #define NP_CMD_IOWRITE (0x3) |
| 64 | #define NP_CMD_MEMREAD (0x6) |
| 65 | #define NP_CMD_MEMWRITE (0x7) |
| 66 | #define NP_CMD_CONFIGREAD (0xa) |
| 67 | #define NP_CMD_CONFIGWRITE (0xb) |
| 68 | */ |
| 69 | |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 70 | /*Configuration Port register bit definitions*/ |
| 71 | #define PCI_CRP_WRITE BIT(16) |
| 72 | |
| 73 | /*ISR (Interrupt status) Register bit definitions*/ |
| 74 | #define PCI_ISR_PSE BIT(0) |
| 75 | #define PCI_ISR_PFE BIT(1) |
| 76 | #define PCI_ISR_PPE BIT(2) |
| 77 | #define PCI_ISR_AHBE BIT(3) |
| 78 | #define PCI_ISR_APDC BIT(4) |
| 79 | #define PCI_ISR_PADC BIT(5) |
| 80 | #define PCI_ISR_ADB BIT(6) |
| 81 | #define PCI_ISR_PDB BIT(7) |
| 82 | |
| 83 | /*INTEN (Interrupt Enable) Register bit definitions*/ |
| 84 | #define PCI_INTEN_PSE BIT(0) |
| 85 | #define PCI_INTEN_PFE BIT(1) |
| 86 | #define PCI_INTEN_PPE BIT(2) |
| 87 | #define PCI_INTEN_AHBE BIT(3) |
| 88 | #define PCI_INTEN_APDC BIT(4) |
| 89 | #define PCI_INTEN_PADC BIT(5) |
| 90 | #define PCI_INTEN_ADB BIT(6) |
| 91 | #define PCI_INTEN_PDB BIT(7) |
| 92 | |
| 93 | /*PCI configuration regs.*/ |
| 94 | |
| 95 | #define PCI_CFG_VENDOR_ID 0x00 |
| 96 | #define PCI_CFG_DEVICE_ID 0x02 |
| 97 | #define PCI_CFG_COMMAND 0x04 |
| 98 | #define PCI_CFG_STATUS 0x06 |
| 99 | #define PCI_CFG_REVISION 0x08 |
| 100 | #define PCI_CFG_PROGRAMMING_IF 0x09 |
| 101 | #define PCI_CFG_SUBCLASS 0x0a |
| 102 | #define PCI_CFG_CLASS 0x0b |
| 103 | #define PCI_CFG_CACHE_LINE_SIZE 0x0c |
| 104 | #define PCI_CFG_LATENCY_TIMER 0x0d |
| 105 | #define PCI_CFG_HEADER_TYPE 0x0e |
| 106 | #define PCI_CFG_BIST 0x0f |
| 107 | #define PCI_CFG_BASE_ADDRESS_0 0x10 |
| 108 | #define PCI_CFG_BASE_ADDRESS_1 0x14 |
| 109 | #define PCI_CFG_BASE_ADDRESS_2 0x18 |
| 110 | #define PCI_CFG_BASE_ADDRESS_3 0x1c |
| 111 | #define PCI_CFG_BASE_ADDRESS_4 0x20 |
| 112 | #define PCI_CFG_BASE_ADDRESS_5 0x24 |
| 113 | #define PCI_CFG_CIS 0x28 |
| 114 | #define PCI_CFG_SUB_VENDOR_ID 0x2c |
| 115 | #define PCI_CFG_SUB_SYSTEM_ID 0x2e |
| 116 | #define PCI_CFG_EXPANSION_ROM 0x30 |
| 117 | #define PCI_CFG_RESERVED_0 0x34 |
| 118 | #define PCI_CFG_RESERVED_1 0x38 |
| 119 | #define PCI_CFG_DEV_INT_LINE 0x3c |
| 120 | #define PCI_CFG_DEV_INT_PIN 0x3d |
| 121 | #define PCI_CFG_MIN_GRANT 0x3e |
| 122 | #define PCI_CFG_MAX_LATENCY 0x3f |
| 123 | #define PCI_CFG_SPECIAL_USE 0x41 |
| 124 | #define PCI_CFG_MODE 0x43 |
| 125 | |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 126 | #define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ |
| 127 | #define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ |
| 128 | #define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ |
| 129 | #define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */ |
| 130 | #define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */ |
| 131 | #define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */ |
| 132 | #define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */ |
| 133 | #define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */ |
| 134 | #define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */ |
| 135 | #define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */ |
| 136 | |
| 137 | |
| 138 | /*CSR Register bit definitions*/ |
| 139 | #define PCI_CSR_HOST BIT(0) |
| 140 | #define PCI_CSR_ARBEN BIT(1) |
| 141 | #define PCI_CSR_ADS BIT(2) |
| 142 | #define PCI_CSR_PDS BIT(3) |
| 143 | #define PCI_CSR_ABE BIT(4) |
| 144 | #define PCI_CSR_DBT BIT(5) |
| 145 | #define PCI_CSR_ASE BIT(8) |
| 146 | #define PCI_CSR_IC BIT(15) |
| 147 | |
| 148 | /*Configuration command bit definitions*/ |
| 149 | #define PCI_CFG_CMD_IOAE BIT(0) |
| 150 | #define PCI_CFG_CMD_MAE BIT(1) |
| 151 | #define PCI_CFG_CMD_BME BIT(2) |
| 152 | #define PCI_CFG_CMD_MWIE BIT(4) |
| 153 | #define PCI_CFG_CMD_SER BIT(8) |
| 154 | #define PCI_CFG_CMD_FBBE BIT(9) |
| 155 | #define PCI_CFG_CMD_MDPE BIT(24) |
| 156 | #define PCI_CFG_CMD_STA BIT(27) |
| 157 | #define PCI_CFG_CMD_RTA BIT(28) |
| 158 | #define PCI_CFG_CMD_RMA BIT(29) |
| 159 | #define PCI_CFG_CMD_SSE BIT(30) |
| 160 | #define PCI_CFG_CMD_DPE BIT(31) |
| 161 | |
| 162 | /*DMACTRL DMA Control and status Register*/ |
| 163 | #define PCI_DMACTRL_APDCEN BIT(0) |
| 164 | #define PCI_DMACTRL_APDC0 BIT(4) |
| 165 | #define PCI_DMACTRL_APDE0 BIT(5) |
| 166 | #define PCI_DMACTRL_APDC1 BIT(6) |
| 167 | #define PCI_DMACTRL_APDE1 BIT(7) |
| 168 | #define PCI_DMACTRL_PADCEN BIT(8) |
| 169 | #define PCI_DMACTRL_PADC0 BIT(12) |
| 170 | #define PCI_DMACTRL_PADE0 BIT(13) |
| 171 | #define PCI_DMACTRL_PADC1 BIT(14) |
| 172 | #define PCI_DMACTRL_PADE1 BIT(15) |
| 173 | |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 174 | #endif |