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Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +05301/*
2 * Xilinx Zynq 7000 DTSI
3 * Describes the hardware common to all Zynq 7000-based boards.
4 *
Michal Simek05e7ca62015-07-22 11:18:43 +02005 * Copyright (C) 2011 - 2015 Xilinx
Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +05306 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "xlnx,zynq-7000";
Masahiro Yamada580a54c2014-05-15 20:37:53 +090013
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 compatible = "arm,cortex-a9";
20 device_type = "cpu";
21 reg = <0>;
22 clocks = <&clkc 3>;
23 clock-latency = <1000>;
Michal Simekbece06c2015-07-22 10:38:45 +020024 cpu0-supply = <&regulator_vccpint>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +090025 operating-points = <
26 /* kHz uV */
27 666667 1000000
28 333334 1000000
Masahiro Yamada580a54c2014-05-15 20:37:53 +090029 >;
30 };
31
32 cpu@1 {
33 compatible = "arm,cortex-a9";
34 device_type = "cpu";
35 reg = <1>;
36 clocks = <&clkc 3>;
37 };
38 };
39
40 pmu {
41 compatible = "arm,cortex-a9-pmu";
42 interrupts = <0 5 4>, <0 6 4>;
43 interrupt-parent = <&intc>;
44 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
45 };
46
Michal Simekbece06c2015-07-22 10:38:45 +020047 regulator_vccpint: fixedregulator@0 {
48 compatible = "regulator-fixed";
49 regulator-name = "VCCPINT";
50 regulator-min-microvolt = <1000000>;
51 regulator-max-microvolt = <1000000>;
52 regulator-boot-on;
53 regulator-always-on;
54 };
55
Michal Simek461c3882015-07-22 11:08:40 +020056 amba: amba {
Simon Glass035c6b22015-10-17 19:41:24 -060057 u-boot,dm-pre-reloc;
Masahiro Yamada580a54c2014-05-15 20:37:53 +090058 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 interrupt-parent = <&intc>;
62 ranges;
63
Michal Simekfb1a5062015-07-22 10:32:05 +020064 adc: adc@f8007100 {
65 compatible = "xlnx,zynq-xadc-1.00.a";
66 reg = <0xf8007100 0x20>;
67 interrupts = <0 7 4>;
68 interrupt-parent = <&intc>;
69 clocks = <&clkc 12>;
70 };
71
72 can0: can@e0008000 {
73 compatible = "xlnx,zynq-can-1.0";
74 status = "disabled";
75 clocks = <&clkc 19>, <&clkc 36>;
76 clock-names = "can_clk", "pclk";
77 reg = <0xe0008000 0x1000>;
78 interrupts = <0 28 4>;
79 interrupt-parent = <&intc>;
80 tx-fifo-depth = <0x40>;
81 rx-fifo-depth = <0x40>;
82 };
83
84 can1: can@e0009000 {
85 compatible = "xlnx,zynq-can-1.0";
86 status = "disabled";
87 clocks = <&clkc 20>, <&clkc 37>;
88 clock-names = "can_clk", "pclk";
89 reg = <0xe0009000 0x1000>;
90 interrupts = <0 51 4>;
91 interrupt-parent = <&intc>;
92 tx-fifo-depth = <0x40>;
93 rx-fifo-depth = <0x40>;
94 };
95
96 gpio0: gpio@e000a000 {
97 compatible = "xlnx,zynq-gpio-1.0";
98 #gpio-cells = <2>;
Michal Simek58fab4c2016-04-07 10:54:08 +020099 #interrupt-cells = <2>;
Michal Simekfb1a5062015-07-22 10:32:05 +0200100 clocks = <&clkc 42>;
101 gpio-controller;
Michal Simek58fab4c2016-04-07 10:54:08 +0200102 interrupt-controller;
Michal Simekfb1a5062015-07-22 10:32:05 +0200103 interrupt-parent = <&intc>;
104 interrupts = <0 20 4>;
105 reg = <0xe000a000 0x1000>;
106 };
107
Michal Simeka0cb47f2015-07-22 10:28:48 +0200108 i2c0: i2c@e0004000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900109 compatible = "cdns,i2c-r1p10";
110 status = "disabled";
111 clocks = <&clkc 38>;
112 interrupt-parent = <&intc>;
113 interrupts = <0 25 4>;
114 reg = <0xe0004000 0x1000>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 };
118
Michal Simeka0cb47f2015-07-22 10:28:48 +0200119 i2c1: i2c@e0005000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900120 compatible = "cdns,i2c-r1p10";
121 status = "disabled";
122 clocks = <&clkc 39>;
123 interrupt-parent = <&intc>;
124 interrupts = <0 48 4>;
125 reg = <0xe0005000 0x1000>;
126 #address-cells = <1>;
127 #size-cells = <0>;
128 };
129
130 intc: interrupt-controller@f8f01000 {
131 compatible = "arm,cortex-a9-gic";
132 #interrupt-cells = <3>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900133 interrupt-controller;
134 reg = <0xF8F01000 0x1000>,
135 <0xF8F00100 0x100>;
136 };
137
Michal Simeka0cb47f2015-07-22 10:28:48 +0200138 L2: cache-controller@f8f02000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900139 compatible = "arm,pl310-cache";
140 reg = <0xF8F02000 0x1000>;
Michal Simekd50cb3d2015-07-22 11:26:08 +0200141 interrupts = <0 2 4>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900142 arm,data-latency = <3 2 2>;
143 arm,tag-latency = <2 2 2>;
144 cache-unified;
145 cache-level = <2>;
146 };
147
Michal Simekfb1a5062015-07-22 10:32:05 +0200148 mc: memory-controller@f8006000 {
149 compatible = "xlnx,zynq-ddrc-a05";
150 reg = <0xf8006000 0x1000>;
151 };
152
Michal Simeka0cb47f2015-07-22 10:28:48 +0200153 uart0: serial@e0000000 {
Michal Simek8a8c46a2015-07-22 10:40:51 +0200154 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900155 status = "disabled";
156 clocks = <&clkc 23>, <&clkc 40>;
Michal Simek8a8c46a2015-07-22 10:40:51 +0200157 clock-names = "uart_clk", "pclk";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900158 reg = <0xE0000000 0x1000>;
159 interrupts = <0 27 4>;
160 };
161
Michal Simeka0cb47f2015-07-22 10:28:48 +0200162 uart1: serial@e0001000 {
Michal Simek8a8c46a2015-07-22 10:40:51 +0200163 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900164 status = "disabled";
165 clocks = <&clkc 24>, <&clkc 41>;
Michal Simek8a8c46a2015-07-22 10:40:51 +0200166 clock-names = "uart_clk", "pclk";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900167 reg = <0xE0001000 0x1000>;
168 interrupts = <0 50 4>;
169 };
170
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530171 spi0: spi@e0006000 {
Michal Simek40b383f2015-07-22 10:47:33 +0200172 compatible = "xlnx,zynq-spi-r1p6";
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530173 reg = <0xe0006000 0x1000>;
174 status = "disabled";
175 interrupt-parent = <&intc>;
176 interrupts = <0 26 4>;
177 clocks = <&clkc 25>, <&clkc 34>;
178 clock-names = "ref_clk", "pclk";
Jagan Tekicdc9dd02015-06-27 00:51:34 +0530179 spi-max-frequency = <166666700>;
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530180 #address-cells = <1>;
181 #size-cells = <0>;
182 };
183
184 spi1: spi@e0007000 {
Michal Simek40b383f2015-07-22 10:47:33 +0200185 compatible = "xlnx,zynq-spi-r1p6";
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530186 reg = <0xe0007000 0x1000>;
187 status = "disabled";
188 interrupt-parent = <&intc>;
189 interrupts = <0 49 4>;
190 clocks = <&clkc 26>, <&clkc 35>;
191 clock-names = "ref_clk", "pclk";
Jagan Tekicdc9dd02015-06-27 00:51:34 +0530192 spi-max-frequency = <166666700>;
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530193 #address-cells = <1>;
194 #size-cells = <0>;
195 };
196
Jagan Teki70676cb2015-08-15 23:02:31 +0530197 qspi: spi@e000d000 {
198 clock-names = "ref_clk", "pclk";
199 clocks = <&clkc 10>, <&clkc 43>;
200 compatible = "xlnx,zynq-qspi-1.0";
201 status = "disabled";
202 interrupt-parent = <&intc>;
203 interrupts = <0 19 4>;
204 reg = <0xe000d000 0x1000>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 };
208
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900209 gem0: ethernet@e000b000 {
Michal Simek7e163362015-07-22 10:51:16 +0200210 compatible = "cdns,zynq-gem", "cdns,gem";
Michal Simek08305fe2015-07-22 10:50:02 +0200211 reg = <0xe000b000 0x1000>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900212 status = "disabled";
213 interrupts = <0 22 4>;
214 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
215 clock-names = "pclk", "hclk", "tx_clk";
Michal Simek5ee236a2015-07-22 11:03:36 +0200216 #address-cells = <1>;
217 #size-cells = <0>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900218 };
219
220 gem1: ethernet@e000c000 {
Michal Simek7e163362015-07-22 10:51:16 +0200221 compatible = "cdns,zynq-gem", "cdns,gem";
Michal Simek08305fe2015-07-22 10:50:02 +0200222 reg = <0xe000c000 0x1000>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900223 status = "disabled";
224 interrupts = <0 45 4>;
225 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
226 clock-names = "pclk", "hclk", "tx_clk";
Michal Simek5ee236a2015-07-22 11:03:36 +0200227 #address-cells = <1>;
228 #size-cells = <0>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900229 };
230
Michal Simeka0cb47f2015-07-22 10:28:48 +0200231 sdhci0: sdhci@e0100000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900232 compatible = "arasan,sdhci-8.9a";
233 status = "disabled";
234 clock-names = "clk_xin", "clk_ahb";
235 clocks = <&clkc 21>, <&clkc 32>;
236 interrupt-parent = <&intc>;
237 interrupts = <0 24 4>;
238 reg = <0xe0100000 0x1000>;
Michal Simeke5c343d2016-01-14 13:06:28 +0100239 };
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900240
Michal Simeka0cb47f2015-07-22 10:28:48 +0200241 sdhci1: sdhci@e0101000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900242 compatible = "arasan,sdhci-8.9a";
243 status = "disabled";
244 clock-names = "clk_xin", "clk_ahb";
245 clocks = <&clkc 22>, <&clkc 33>;
246 interrupt-parent = <&intc>;
247 interrupts = <0 47 4>;
248 reg = <0xe0101000 0x1000>;
Michal Simeke5c343d2016-01-14 13:06:28 +0100249 };
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900250
251 slcr: slcr@f8000000 {
252 #address-cells = <1>;
253 #size-cells = <1>;
Masahiro Yamada621a93e2016-04-25 12:14:43 +0900254 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900255 reg = <0xF8000000 0x1000>;
256 ranges;
257 clkc: clkc@100 {
258 #clock-cells = <1>;
259 compatible = "xlnx,ps7-clkc";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900260 fclk-enable = <0>;
261 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
262 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
263 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
264 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
265 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
266 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
267 "gem1_aper", "sdio0_aper", "sdio1_aper",
268 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
269 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
270 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
271 "dbg_trc", "dbg_apb";
272 reg = <0x100 0x100>;
273 };
Michal Simeke913ce22015-07-22 11:07:49 +0200274
Moritz Fischer4c987272015-07-30 18:13:55 -0700275 rstc: rstc@200 {
276 compatible = "xlnx,zynq-reset";
277 reg = <0x200 0x48>;
278 #reset-cells = <1>;
279 syscon = <&slcr>;
280 };
281
Michal Simeke913ce22015-07-22 11:07:49 +0200282 pinctrl0: pinctrl@700 {
283 compatible = "xlnx,pinctrl-zynq";
284 reg = <0x700 0x200>;
285 syscon = <&slcr>;
286 };
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900287 };
288
Michal Simekfb1a5062015-07-22 10:32:05 +0200289 dmac_s: dmac@f8003000 {
290 compatible = "arm,pl330", "arm,primecell";
291 reg = <0xf8003000 0x1000>;
292 interrupt-parent = <&intc>;
293 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
294 "dma4", "dma5", "dma6", "dma7";
295 interrupts = <0 13 4>,
296 <0 14 4>, <0 15 4>,
297 <0 16 4>, <0 17 4>,
298 <0 40 4>, <0 41 4>,
299 <0 42 4>, <0 43 4>;
300 #dma-cells = <1>;
301 #dma-channels = <8>;
302 #dma-requests = <4>;
303 clocks = <&clkc 27>;
304 clock-names = "apb_pclk";
305 };
306
307 devcfg: devcfg@f8007000 {
308 compatible = "xlnx,zynq-devcfg-1.0";
Michal Simek77bb73d2016-04-07 11:00:37 +0200309 interrupt-parent = <&intc>;
310 interrupts = <0 8 4>;
Michal Simekfb1a5062015-07-22 10:32:05 +0200311 reg = <0xf8007000 0x100>;
Michal Simek77bb73d2016-04-07 11:00:37 +0200312 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
313 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
Moritz Fischer20fe3f12015-06-22 23:18:44 -0700314 syscon = <&slcr>;
Michal Simekfb1a5062015-07-22 10:32:05 +0200315 };
316
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900317 global_timer: timer@f8f00200 {
318 compatible = "arm,cortex-a9-global-timer";
319 reg = <0xf8f00200 0x20>;
320 interrupts = <1 11 0x301>;
321 interrupt-parent = <&intc>;
322 clocks = <&clkc 4>;
323 };
324
Michal Simeka0cb47f2015-07-22 10:28:48 +0200325 ttc0: timer@f8001000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900326 interrupt-parent = <&intc>;
Michal Simekb346bd12015-07-22 10:57:51 +0200327 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900328 compatible = "cdns,ttc";
329 clocks = <&clkc 6>;
330 reg = <0xF8001000 0x1000>;
331 };
332
Michal Simeka0cb47f2015-07-22 10:28:48 +0200333 ttc1: timer@f8002000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900334 interrupt-parent = <&intc>;
Michal Simekb346bd12015-07-22 10:57:51 +0200335 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900336 compatible = "cdns,ttc";
337 clocks = <&clkc 6>;
338 reg = <0xF8002000 0x1000>;
339 };
Michal Simekfb1a5062015-07-22 10:32:05 +0200340
Michal Simeka0cb47f2015-07-22 10:28:48 +0200341 scutimer: timer@f8f00600 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900342 interrupt-parent = <&intc>;
Michal Simeke5c343d2016-01-14 13:06:28 +0100343 interrupts = <1 13 0x301>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900344 compatible = "arm,cortex-a9-twd-timer";
Michal Simeke5c343d2016-01-14 13:06:28 +0100345 reg = <0xf8f00600 0x20>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900346 clocks = <&clkc 4>;
Michal Simeke5c343d2016-01-14 13:06:28 +0100347 };
Michal Simekfb1a5062015-07-22 10:32:05 +0200348
349 usb0: usb@e0002000 {
350 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
351 status = "disabled";
352 clocks = <&clkc 28>;
353 interrupt-parent = <&intc>;
354 interrupts = <0 21 4>;
355 reg = <0xe0002000 0x1000>;
356 phy_type = "ulpi";
357 };
358
359 usb1: usb@e0003000 {
360 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
361 status = "disabled";
362 clocks = <&clkc 29>;
363 interrupt-parent = <&intc>;
364 interrupts = <0 44 4>;
365 reg = <0xe0003000 0x1000>;
366 phy_type = "ulpi";
367 };
368
369 watchdog0: watchdog@f8005000 {
370 clocks = <&clkc 45>;
371 compatible = "cdns,wdt-r1p2";
372 interrupt-parent = <&intc>;
373 interrupts = <0 9 1>;
374 reg = <0xf8005000 0x1000>;
375 timeout-sec = <10>;
376 };
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900377 };
Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +0530378};