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Stefan Roese899620c2006-08-15 14:22:35 +02001/*
Stefan Roese5bc528f2006-10-07 11:35:25 +02002 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
Stefan Roese899620c2006-08-15 14:22:35 +020023
24#include <ppc_asm.tmpl>
25#include <config.h>
26
27/* General */
28#define TLB_VALID 0x00000200
29
30/* Supported page sizes */
Stefan Roese899620c2006-08-15 14:22:35 +020031#define SZ_1K 0x00000000
32#define SZ_4K 0x00000010
33#define SZ_16K 0x00000020
34#define SZ_64K 0x00000030
Stefan Roese5bc528f2006-10-07 11:35:25 +020035#define SZ_256K 0x00000040
Stefan Roese899620c2006-08-15 14:22:35 +020036#define SZ_1M 0x00000050
37#define SZ_16M 0x00000070
Stefan Roese5bc528f2006-10-07 11:35:25 +020038#define SZ_256M 0x00000090
Stefan Roese899620c2006-08-15 14:22:35 +020039
40/* Storage attributes */
41#define SA_W 0x00000800 /* Write-through */
42#define SA_I 0x00000400 /* Caching inhibited */
43#define SA_M 0x00000200 /* Memory coherence */
44#define SA_G 0x00000100 /* Guarded */
45#define SA_E 0x00000080 /* Endian */
46
47/* Access control */
48#define AC_X 0x00000024 /* Execute */
49#define AC_W 0x00000012 /* Write */
50#define AC_R 0x00000009 /* Read */
51
52/* Some handy macros */
53
54#define EPN(e) ((e) & 0xfffffc00)
55#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
56#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
57#define TLB2(a) ( (a)&0x00000fbf )
58
59#define tlbtab_start\
60 mflr r1 ;\
61 bl 0f ;
62
63#define tlbtab_end\
64 .long 0, 0, 0 ; \
650: mflr r0 ; \
66 mtlr r1 ; \
67 blr ;
68
69#define tlbentry(epn,sz,rpn,erpn,attr)\
70 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
71
72
73/**************************************************************************
74 * TLB TABLE
75 *
76 * This table is used by the cpu boot code to setup the initial tlb
77 * entries. Rather than make broad assumptions in the cpu source tree,
78 * this table lets each board set things up however they like.
79 *
80 * Pointer to the table is returned in r1
81 *
82 *************************************************************************/
83
Stefan Roese5bc528f2006-10-07 11:35:25 +020084 .section .bootpg,"ax"
85 .globl tlbtab
Stefan Roese899620c2006-08-15 14:22:35 +020086
87tlbtab:
Stefan Roese5bc528f2006-10-07 11:35:25 +020088 tlbtab_start
89 tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090 tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
91 tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
92 tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +010093#ifdef CONFIG_4xx_DCACHE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +010095#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +010097#endif
98
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +0100100 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101 tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +0100102#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103 tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
Stefan Roese899620c2006-08-15 14:22:35 +0200104
Stefan Roese5bc528f2006-10-07 11:35:25 +0200105 /* PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
107 tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
108 tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
Stefan Roese5bc528f2006-10-07 11:35:25 +0200109
110 /* NAND */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 tlbentry( CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
Stefan Roese5bc528f2006-10-07 11:35:25 +0200112 tlbtab_end