blob: 72a1ad32f7a98e4c49e809c87327d7fc98535f18 [file] [log] [blame]
Lunsheng Wangb0e32942005-07-29 10:20:29 -05001/*
2 * (C) Copyright 2002,2003, Motorola Inc.
3 * Xianghua Xiao, (X.Xiao@motorola.com)
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
Lunsheng Wangb0e32942005-07-29 10:20:29 -050026#include <common.h>
Ben Warren8ca0b3f2008-08-31 10:45:44 -070027#include <netdev.h>
Lunsheng Wangb0e32942005-07-29 10:20:29 -050028#include <asm/processor.h>
Kumar Gala9658bec2008-08-26 23:52:32 -050029#include <asm/mmu.h>
Lunsheng Wangb0e32942005-07-29 10:20:29 -050030#include <asm/immap_85xx.h>
Kumar Gala9658bec2008-08-26 23:52:32 -050031#include <asm/fsl_ddr_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060032#include <spd_sdram.h>
Lunsheng Wangb0e32942005-07-29 10:20:29 -050033
34long int fixed_sdram (void);
35
Lunsheng Wangb0e32942005-07-29 10:20:29 -050036int board_pre_init (void)
37{
38#if defined(CONFIG_PCI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039 volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
Lunsheng Wangb0e32942005-07-29 10:20:29 -050040
41 pci->peer &= 0xffffffdf; /* disable master abort */
42#endif
43 return 0;
44}
45
46int checkboard (void)
47{
48 sys_info_t sysinfo;
49
50 get_sys_info (&sysinfo);
51
52 printf ("Board: Freescale MPC8540EVAL Board\n");
Kumar Gala9cda4f12009-01-28 08:31:10 -060053 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor[0] / 1000000);
Lunsheng Wangb0e32942005-07-29 10:20:29 -050054 printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
55 printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056 if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
57 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
Jon Loeligerde1d0a62005-08-01 13:20:47 -050058 printf ("\tLBC: %lu MHz\n",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059 sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));
Lunsheng Wangb0e32942005-07-29 10:20:29 -050060 } else {
61 printf("\tLBC: unknown\n");
62 }
63 printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
64 return (0);
65}
66
Becky Bruce9973e3c2008-06-09 16:03:40 -050067phys_size_t initdram (int board_type)
Lunsheng Wangb0e32942005-07-29 10:20:29 -050068{
69 long dram_size = 0;
Jon Loeligera30a5492008-03-04 10:03:03 -060070
Lunsheng Wangb0e32942005-07-29 10:20:29 -050071#if !defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
Lunsheng Wangb0e32942005-07-29 10:20:29 -050073 sys_info_t sysinfo;
74 uint temp_lbcdll = 0;
75#endif
76#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Lunsheng Wangb0e32942005-07-29 10:20:29 -050078#endif
79
80#if defined(CONFIG_DDR_DLL)
81 uint temp_ddrdll = 0;
82
83 /* Work around to stabilize DDR DLL */
84 temp_ddrdll = gur->ddrdllcr;
85 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
86 asm("sync;isync;msync");
87#endif
88
89#if defined(CONFIG_SPD_EEPROM)
Kumar Gala9658bec2008-08-26 23:52:32 -050090 dram_size = fsl_ddr_sdram();
91 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
92 dram_size *= 0x100000;
Lunsheng Wangb0e32942005-07-29 10:20:29 -050093#else
94 dram_size = fixed_sdram ();
95#endif
96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#if defined(CONFIG_SYS_RAMBOOT)
Lunsheng Wangb0e32942005-07-29 10:20:29 -050098 return dram_size;
99#endif
100
101#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
102 get_sys_info(&sysinfo);
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200103 /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
Trent Piephoa5d212a2008-12-03 15:16:34 -0800104 if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105 lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500106 } else {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107 lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500108 udelay(200);
109 temp_lbcdll = gur->lbcdllcr;
110 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
111 asm("sync;isync;msync");
112 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
114 lbc->br2 = CONFIG_SYS_BR2_PRELIM;
115 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
116 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500117 asm("sync");
118 * (ulong *)0 = 0x000000ff;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500120 asm("sync");
121 * (ulong *)0 = 0x000000ff;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500123 asm("sync");
124 * (ulong *)0 = 0x000000ff;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500126 asm("sync");
127 * (ulong *)0 = 0x000000ff;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500129 asm("sync");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500131 asm("sync");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500133 asm("sync");
134#endif
135
136#if defined(CONFIG_DDR_ECC)
137 {
138 /* Initialize all of memory for ECC, then
139 * enable errors */
140 uint *p = 0;
141 uint i = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500143 dma_init();
144 for (*p = 0; p < (uint *)(8 * 1024); p++) {
145 if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
146 *p = (unsigned int)0xdeadbeef;
147 if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
148 }
149
150 /* 8K */
151 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
152 /* 16K */
153 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
154 /* 32K */
155 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
156 /* 64K */
157 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
158 /* 128k */
159 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
160 /* 256k */
161 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
162 /* 512k */
163 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
164 /* 1M */
165 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
166 /* 2M */
167 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
168 /* 4M */
169 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
170
171 for (i = 1; i < dram_size / 0x800000; i++) {
172 dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
173 }
174
175 /* Enable errors for ECC */
176 ddr->err_disable = 0x00000000;
177 asm("sync;isync;msync");
178 }
179#endif
180
181 return dram_size;
182}
183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#if defined(CONFIG_SYS_DRAM_TEST)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500185int testdram (void)
186{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
188 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500189 uint *p;
190
191 printf("SDRAM test phase 1:\n");
192 for (p = pstart; p < pend; p++)
193 *p = 0xaaaaaaaa;
194
195 for (p = pstart; p < pend; p++) {
196 if (*p != 0xaaaaaaaa) {
197 printf ("SDRAM test fails at: %08x\n", (uint) p);
198 return 1;
199 }
200 }
201
202 printf("SDRAM test phase 2:\n");
203 for (p = pstart; p < pend; p++)
204 *p = 0x55555555;
205
206 for (p = pstart; p < pend; p++) {
207 if (*p != 0x55555555) {
208 printf ("SDRAM test fails at: %08x\n", (uint) p);
209 return 1;
210 }
211 }
212
213 printf("SDRAM test passed.\n");
214 return 0;
215}
216#endif
217
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500218#if !defined(CONFIG_SPD_EEPROM)
219/*************************************************************************
220 * fixed sdram init -- doesn't use serial presence detect.
221 ************************************************************************/
222long int fixed_sdram (void)
223{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#ifndef CONFIG_SYS_RAMBOOT
225 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
228 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
229 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
230 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
231 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
232 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500233#if defined (CONFIG_DDR_ECC)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500234 ddr->err_disable = 0x0000000D;
235 ddr->err_sbe = 0x00ff0000;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500236#endif
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500237 asm("sync;isync;msync");
238 udelay(500);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500239#if defined (CONFIG_DDR_ECC)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500240 /* Enable ECC checking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500242#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500244#endif
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500245 asm("sync; isync; msync");
246 udelay(500);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500247#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248 return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500249}
250#endif /* !defined(CONFIG_SPD_EEPROM) */
Ben Warren8ca0b3f2008-08-31 10:45:44 -0700251
252int board_eth_init(bd_t *bis)
253{
254 /*
255 * This board either has PCI NICs or uses the CPU's TSECs
256 * pci_eth_init() will return 0 if no NICs found, so in that case
257 * returning -1 will force cpu_eth_init() to be called.
258 */
259 int num = pci_eth_init(bis);
260 return (num <= 0 ? -1 : num);
261}