blob: 704dc630d3ac1f962fde32edd95efc63fd01d9d1 [file] [log] [blame]
Kyle Moffettf8bbb4d2011-12-07 16:39:16 -05001/*
2 * Copyright 2010 eXMeritus, A Boeing Company
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kyle Moffettf8bbb4d2011-12-07 16:39:16 -05005 */
6
7#include <asm/mpc85xx_gpio.h>
8
9/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */
10#define GPIO_CPU_ID (1UL << (31 - 8))
11#define GPIO_BLUE_LED (1UL << (31 - 9))
12#define GPIO_DIMM_RESET (1UL << (31 - 10))
13#define GPIO_USB_RESET (1UL << (31 - 11))
14#define GPIO_UNUSED_12 (1UL << (31 - 12))
15#define GPIO_GETH0_RESET (1UL << (31 - 13))
16#define GPIO_RS422_RE (1UL << (31 - 14))
17#define GPIO_RS422_DE (1UL << (31 - 15))
18#define IRQ_I2CINT (1UL << (31 - 20))
19#define IRQ_FANINT (1UL << (31 - 21))
20#define IRQ_DIMM_EVENT (1UL << (31 - 22))
21
22#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET)
23
24/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
25#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0))
26#define GPIO_CPUA_CPU_READY (1UL << (31 - 1))
27#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2))
28#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3))
29#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */
30#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */
31#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */
32#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */
33#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16))
34#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17))
35#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18))
36#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19))
37
38/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
39#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0))
40#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1))
41#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2))
42#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3))
43#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4))
44#define GPIO_CPUB_CPU_READY (1UL << (31 - 5))
45#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6))
46#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7))
47#define IRQ_CPUB_SD_1A (1UL << (31 - 16))
48#define IRQ_CPUB_SD_2B (1UL << (31 - 17))
49#define IRQ_CPUB_SD_2A (1UL << (31 - 18))
50#define IRQ_CPUB_SD_1B (1UL << (31 - 19))
51
52/* If it isn't CPU A then it's CPU B */
53static inline unsigned int hww1u1a_is_cpu_a(void)
54{
55 return !mpc85xx_gpio_get(GPIO_CPU_ID);
56}