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Simon Glass18530302013-03-19 04:58:56 +00001/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Simon Glass18530302013-03-19 04:58:56 +00005 *
6 * This file is derived from the flashrom project.
7 */
8
Bin Meng9eb43392016-02-01 01:40:36 -08009#ifndef _ICH_H_
10#define _ICH_H_
11
Simon Glass18530302013-03-19 04:58:56 +000012struct ich7_spi_regs {
13 uint16_t spis;
14 uint16_t spic;
15 uint32_t spia;
16 uint64_t spid[8];
17 uint64_t _pad;
18 uint32_t bbar;
19 uint16_t preop;
20 uint16_t optype;
21 uint8_t opmenu[8];
22} __packed;
23
24struct ich9_spi_regs {
Bin Meng9eb43392016-02-01 01:40:36 -080025 uint32_t bfpr; /* 0x00 */
Simon Glass18530302013-03-19 04:58:56 +000026 uint16_t hsfs;
27 uint16_t hsfc;
28 uint32_t faddr;
29 uint32_t _reserved0;
Bin Meng9eb43392016-02-01 01:40:36 -080030 uint32_t fdata[16]; /* 0x10 */
31 uint32_t frap; /* 0x50 */
Simon Glass18530302013-03-19 04:58:56 +000032 uint32_t freg[5];
33 uint32_t _reserved1[3];
Bin Meng9eb43392016-02-01 01:40:36 -080034 uint32_t pr[5]; /* 0x74 */
Simon Glass18530302013-03-19 04:58:56 +000035 uint32_t _reserved2[2];
Bin Meng9eb43392016-02-01 01:40:36 -080036 uint8_t ssfs; /* 0x90 */
Simon Glass18530302013-03-19 04:58:56 +000037 uint8_t ssfc[3];
Bin Meng9eb43392016-02-01 01:40:36 -080038 uint16_t preop; /* 0x94 */
Simon Glass18530302013-03-19 04:58:56 +000039 uint16_t optype;
Bin Meng9eb43392016-02-01 01:40:36 -080040 uint8_t opmenu[8]; /* 0x98 */
Simon Glass18530302013-03-19 04:58:56 +000041 uint32_t bbar;
42 uint8_t _reserved3[12];
Bin Meng9eb43392016-02-01 01:40:36 -080043 uint32_t fdoc; /* 0xb0 */
Simon Glass18530302013-03-19 04:58:56 +000044 uint32_t fdod;
45 uint8_t _reserved4[8];
Bin Meng9eb43392016-02-01 01:40:36 -080046 uint32_t afc; /* 0xc0 */
Simon Glass18530302013-03-19 04:58:56 +000047 uint32_t lvscc;
48 uint32_t uvscc;
49 uint8_t _reserved5[4];
Bin Meng9eb43392016-02-01 01:40:36 -080050 uint32_t fpb; /* 0xd0 */
Simon Glass18530302013-03-19 04:58:56 +000051 uint8_t _reserved6[28];
Bin Meng9eb43392016-02-01 01:40:36 -080052 uint32_t srdl; /* 0xf0 */
Simon Glass18530302013-03-19 04:58:56 +000053 uint32_t srdc;
Simon Glass5093bad2015-01-27 22:13:43 -070054 uint32_t scs;
55 uint32_t bcr;
Simon Glass18530302013-03-19 04:58:56 +000056} __packed;
57
58enum {
59 SPIS_SCIP = 0x0001,
60 SPIS_GRANT = 0x0002,
61 SPIS_CDS = 0x0004,
62 SPIS_FCERR = 0x0008,
63 SSFS_AEL = 0x0010,
64 SPIS_LOCK = 0x8000,
65 SPIS_RESERVED_MASK = 0x7ff0,
66 SSFS_RESERVED_MASK = 0x7fe2
67};
68
69enum {
70 SPIC_SCGO = 0x000002,
71 SPIC_ACS = 0x000004,
72 SPIC_SPOP = 0x000008,
73 SPIC_DBC = 0x003f00,
74 SPIC_DS = 0x004000,
75 SPIC_SME = 0x008000,
76 SSFC_SCF_MASK = 0x070000,
77 SSFC_RESERVED = 0xf80000,
78
79 /* Mask for speed byte, biuts 23:16 of SSFC */
80 SSFC_SCF_33MHZ = 0x01,
81};
82
83enum {
84 HSFS_FDONE = 0x0001,
85 HSFS_FCERR = 0x0002,
86 HSFS_AEL = 0x0004,
87 HSFS_BERASE_MASK = 0x0018,
88 HSFS_BERASE_SHIFT = 3,
89 HSFS_SCIP = 0x0020,
90 HSFS_FDOPSS = 0x2000,
91 HSFS_FDV = 0x4000,
92 HSFS_FLOCKDN = 0x8000
93};
94
95enum {
96 HSFC_FGO = 0x0001,
97 HSFC_FCYCLE_MASK = 0x0006,
98 HSFC_FCYCLE_SHIFT = 1,
99 HSFC_FDBC_MASK = 0x3f00,
100 HSFC_FDBC_SHIFT = 8,
101 HSFC_FSMIE = 0x8000
102};
103
104enum {
Simon Glass18530302013-03-19 04:58:56 +0000105 ICH_MAX_CMD_LEN = 5,
106};
107
108struct spi_trans {
109 uint8_t cmd[ICH_MAX_CMD_LEN];
110 int cmd_len;
111 const uint8_t *out;
112 uint32_t bytesout;
113 uint8_t *in;
114 uint32_t bytesin;
115 uint8_t type;
116 uint8_t opcode;
117 uint32_t offset;
118};
119
Stefan Roese4759dff2017-04-24 09:48:04 +0200120#define SPI_OPCODE_WRSR 0x01
121#define SPI_OPCODE_PAGE_PROGRAM 0x02
122#define SPI_OPCODE_READ 0x03
123#define SPI_OPCODE_WRDIS 0x04
124#define SPI_OPCODE_RDSR 0x05
Bin Meng9eb43392016-02-01 01:40:36 -0800125#define SPI_OPCODE_WREN 0x06
126#define SPI_OPCODE_FAST_READ 0x0b
Stefan Roese4759dff2017-04-24 09:48:04 +0200127#define SPI_OPCODE_ERASE_SECT 0x20
128#define SPI_OPCODE_READ_ID 0x9f
129#define SPI_OPCODE_ERASE_BLOCK 0xd8
130
131#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
132#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
133#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
134#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
135
136#define SPI_OPMENU_0 SPI_OPCODE_WRSR
137#define SPI_OPTYPE_0 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
138
139#define SPI_OPMENU_1 SPI_OPCODE_PAGE_PROGRAM
140#define SPI_OPTYPE_1 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
141
142#define SPI_OPMENU_2 SPI_OPCODE_READ
143#define SPI_OPTYPE_2 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
144
145#define SPI_OPMENU_3 SPI_OPCODE_RDSR
146#define SPI_OPTYPE_3 SPI_OPCODE_TYPE_READ_NO_ADDRESS
147
148#define SPI_OPMENU_4 SPI_OPCODE_ERASE_SECT
149#define SPI_OPTYPE_4 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
150
151#define SPI_OPMENU_5 SPI_OPCODE_READ_ID
152#define SPI_OPTYPE_5 SPI_OPCODE_TYPE_READ_NO_ADDRESS
153
154#define SPI_OPMENU_6 SPI_OPCODE_ERASE_BLOCK
155#define SPI_OPTYPE_6 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
156
157#define SPI_OPMENU_7 SPI_OPCODE_FAST_READ
158#define SPI_OPTYPE_7 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
159
160#define SPI_OPPREFIX ((SPI_OPCODE_WREN << 8) | SPI_OPCODE_WREN)
161#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
162 (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
163 (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
164 (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
165#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
166 (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
167#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
168 (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
Bin Meng9eb43392016-02-01 01:40:36 -0800169
Bin Meng6e670b52016-02-01 01:40:38 -0800170enum ich_version {
171 ICHV_7,
172 ICHV_9,
173};
174
Bin Meng9eb43392016-02-01 01:40:36 -0800175struct ich_spi_platdata {
Bin Meng6e670b52016-02-01 01:40:38 -0800176 enum ich_version ich_version; /* Controller version, 7 or 9 */
Simon Glass18530302013-03-19 04:58:56 +0000177};
Bin Meng9eb43392016-02-01 01:40:36 -0800178
179struct ich_spi_priv {
Bin Meng9eb43392016-02-01 01:40:36 -0800180 int opmenu;
181 int menubytes;
182 void *base; /* Base of register set */
183 int preop;
184 int optype;
185 int addr;
186 int data;
187 unsigned databytes;
188 int status;
189 int control;
190 int bbar;
191 int bcr;
192 uint32_t *pr; /* only for ich9 */
193 int speed; /* pointer to speed control */
194 ulong max_speed; /* Maximum bus speed in MHz */
195 ulong cur_speed; /* Current bus speed */
196 struct spi_trans trans; /* current transaction in progress */
197};
198
199#endif /* _ICH_H_ */