blob: 324f7108d5a12cf16988018e5359ac26b0da4c08 [file] [log] [blame]
Shengzhou Liu48c6f322014-11-24 17:11:56 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T1024/T1023 RDB board configuration file
9 */
10
11#ifndef __T1024RDB_H
12#define __T1024RDB_H
13
14/* High Level Configuration Options */
15#define CONFIG_SYS_GENERIC_BOARD
16#define CONFIG_DISPLAY_BOARDINFO
17#define CONFIG_BOOKE
18#define CONFIG_E500 /* BOOKE e500 family */
19#define CONFIG_E500MC /* BOOKE e500mc family */
20#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
21#define CONFIG_MP /* support multiple processors */
22#define CONFIG_PHYS_64BIT
23#define CONFIG_ENABLE_36BIT_PHYS
24
25#ifdef CONFIG_PHYS_64BIT
26#define CONFIG_ADDR_MAP 1
27#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
28#endif
29
30#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
31#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
32#define CONFIG_FSL_IFC /* Enable IFC Support */
33
34#define CONFIG_FSL_LAW /* Use common FSL init code */
35#define CONFIG_ENV_OVERWRITE
36
37/* support deep sleep */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080038#ifdef CONFIG_PPC_T1024
Shengzhou Liu48c6f322014-11-24 17:11:56 +080039#define CONFIG_DEEP_SLEEP
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080040#endif
tang yuantianf49b8c12014-12-17 15:42:54 +080041#if defined(CONFIG_DEEP_SLEEP)
Shengzhou Liu48c6f322014-11-24 17:11:56 +080042#define CONFIG_SILENT_CONSOLE
tang yuantianf49b8c12014-12-17 15:42:54 +080043#define CONFIG_BOARD_EARLY_INIT_F
44#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +080045
46#ifdef CONFIG_RAMBOOT_PBL
47#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080048#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +080049#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080050#elif defined(CONFIG_T1023RDB)
51#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
52#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +080053#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
54#define CONFIG_SPL_ENV_SUPPORT
55#define CONFIG_SPL_SERIAL_SUPPORT
56#define CONFIG_SPL_FLUSH_IMAGE
57#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
58#define CONFIG_SPL_LIBGENERIC_SUPPORT
59#define CONFIG_SPL_LIBCOMMON_SUPPORT
60#define CONFIG_SPL_I2C_SUPPORT
61#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
62#define CONFIG_FSL_LAW /* Use common FSL init code */
tang yuantianf49b8c12014-12-17 15:42:54 +080063#define CONFIG_SYS_TEXT_BASE 0x30001000
Shengzhou Liu48c6f322014-11-24 17:11:56 +080064#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
65#define CONFIG_SPL_PAD_TO 0x40000
66#define CONFIG_SPL_MAX_SIZE 0x28000
67#define RESET_VECTOR_OFFSET 0x27FFC
68#define BOOT_PAGE_OFFSET 0x27000
69#ifdef CONFIG_SPL_BUILD
70#define CONFIG_SPL_SKIP_RELOCATE
71#define CONFIG_SPL_COMMON_INIT_DDR
72#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
73#define CONFIG_SYS_NO_FLASH
74#endif
75
76#ifdef CONFIG_NAND
77#define CONFIG_SPL_NAND_SUPPORT
78#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
tang yuantianf49b8c12014-12-17 15:42:54 +080079#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
80#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
Shengzhou Liu48c6f322014-11-24 17:11:56 +080081#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
82#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
83#define CONFIG_SPL_NAND_BOOT
84#endif
85
86#ifdef CONFIG_SPIFLASH
tang yuantianf49b8c12014-12-17 15:42:54 +080087#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Shengzhou Liu48c6f322014-11-24 17:11:56 +080088#define CONFIG_SPL_SPI_SUPPORT
89#define CONFIG_SPL_SPI_FLASH_SUPPORT
90#define CONFIG_SPL_SPI_FLASH_MINIMAL
91#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
tang yuantianf49b8c12014-12-17 15:42:54 +080092#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
93#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
Shengzhou Liu48c6f322014-11-24 17:11:56 +080094#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
95#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
96#ifndef CONFIG_SPL_BUILD
97#define CONFIG_SYS_MPC85XX_NO_RESETVEC
98#endif
99#define CONFIG_SPL_SPI_BOOT
100#endif
101
102#ifdef CONFIG_SDCARD
tang yuantianf49b8c12014-12-17 15:42:54 +0800103#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800104#define CONFIG_SPL_MMC_SUPPORT
105#define CONFIG_SPL_MMC_MINIMAL
106#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
tang yuantianf49b8c12014-12-17 15:42:54 +0800107#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
108#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800109#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
110#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
111#ifndef CONFIG_SPL_BUILD
112#define CONFIG_SYS_MPC85XX_NO_RESETVEC
113#endif
114#define CONFIG_SPL_MMC_BOOT
115#endif
116
117#endif /* CONFIG_RAMBOOT_PBL */
118
119#ifndef CONFIG_SYS_TEXT_BASE
120#define CONFIG_SYS_TEXT_BASE 0xeff40000
121#endif
122
123#ifndef CONFIG_RESET_VECTOR_ADDRESS
124#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
125#endif
126
127#ifndef CONFIG_SYS_NO_FLASH
128#define CONFIG_FLASH_CFI_DRIVER
129#define CONFIG_SYS_FLASH_CFI
130#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
131#endif
132
133/* PCIe Boot - Master */
134#define CONFIG_SRIO_PCIE_BOOT_MASTER
135/*
136 * for slave u-boot IMAGE instored in master memory space,
137 * PHYS must be aligned based on the SIZE
138 */
139#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
140#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
141#ifdef CONFIG_PHYS_64BIT
142#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
143#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
144#else
145#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
146#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
147#endif
148/*
149 * for slave UCODE and ENV instored in master memory space,
150 * PHYS must be aligned based on the SIZE
151 */
152#ifdef CONFIG_PHYS_64BIT
153#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
154#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
155#else
156#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
157#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
158#endif
159#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
160/* slave core release by master*/
161#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
162#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
163
164/* PCIe Boot - Slave */
165#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
166#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
167#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
168 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
169/* Set 1M boot space for PCIe boot */
170#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
171#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
172 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
173#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
174#define CONFIG_SYS_NO_FLASH
175#endif
176
177#if defined(CONFIG_SPIFLASH)
178#define CONFIG_SYS_EXTRA_ENV_RELOC
179#define CONFIG_ENV_IS_IN_SPI_FLASH
180#define CONFIG_ENV_SPI_BUS 0
181#define CONFIG_ENV_SPI_CS 0
182#define CONFIG_ENV_SPI_MAX_HZ 10000000
183#define CONFIG_ENV_SPI_MODE 0
184#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
185#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800186#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800187#define CONFIG_ENV_SECT_SIZE 0x10000
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800188#elif defined(CONFIG_T1023RDB)
189#define CONFIG_ENV_SECT_SIZE 0x40000
190#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800191#elif defined(CONFIG_SDCARD)
192#define CONFIG_SYS_EXTRA_ENV_RELOC
193#define CONFIG_ENV_IS_IN_MMC
194#define CONFIG_SYS_MMC_ENV_DEV 0
195#define CONFIG_ENV_SIZE 0x2000
196#define CONFIG_ENV_OFFSET (512 * 0x800)
197#elif defined(CONFIG_NAND)
198#define CONFIG_SYS_EXTRA_ENV_RELOC
199#define CONFIG_ENV_IS_IN_NAND
200#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800201#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800202#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800203#elif defined(CONFIG_T1023RDB)
204#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
205#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800206#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
207#define CONFIG_ENV_IS_IN_REMOTE
208#define CONFIG_ENV_ADDR 0xffe20000
209#define CONFIG_ENV_SIZE 0x2000
210#elif defined(CONFIG_ENV_IS_NOWHERE)
211#define CONFIG_ENV_SIZE 0x2000
212#else
213#define CONFIG_ENV_IS_IN_FLASH
214#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
215#define CONFIG_ENV_SIZE 0x2000
216#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
217#endif
218
219
220#ifndef __ASSEMBLY__
221unsigned long get_board_sys_clk(void);
222unsigned long get_board_ddr_clk(void);
223#endif
224
225#define CONFIG_SYS_CLK_FREQ 100000000
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800226#define CONFIG_DDR_CLK_FREQ 100000000
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800227
228/*
229 * These can be toggled for performance analysis, otherwise use default.
230 */
231#define CONFIG_SYS_CACHE_STASHING
232#define CONFIG_BACKSIDE_L2_CACHE
233#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
234#define CONFIG_BTB /* toggle branch predition */
235#define CONFIG_DDR_ECC
236#ifdef CONFIG_DDR_ECC
237#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
238#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
239#endif
240
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800241#define CONFIG_CMD_MEMTEST
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800242#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
243#define CONFIG_SYS_MEMTEST_END 0x00400000
244#define CONFIG_SYS_ALT_MEMTEST
245#define CONFIG_PANIC_HANG /* do not reset board on panic */
246
247/*
248 * Config the L3 Cache as L3 SRAM
249 */
250#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
251#define CONFIG_SYS_L3_SIZE (256 << 10)
252#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
253#ifdef CONFIG_RAMBOOT_PBL
254#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
255#endif
256#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
257#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
258#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
259#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
260
261#ifdef CONFIG_PHYS_64BIT
262#define CONFIG_SYS_DCSRBAR 0xf0000000
263#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
264#endif
265
266/* EEPROM */
267#define CONFIG_ID_EEPROM
268#define CONFIG_SYS_I2C_EEPROM_NXID
269#define CONFIG_SYS_EEPROM_BUS_NUM 0
270#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
271#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
272#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
273#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
274
275/*
276 * DDR Setup
277 */
278#define CONFIG_VERY_BIG_RAM
279#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
280#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
281#define CONFIG_DIMM_SLOTS_PER_CTLR 1
282#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800283#define CONFIG_FSL_DDR_INTERACTIVE
284#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800285#define CONFIG_DDR_SPD
286#define CONFIG_SYS_FSL_DDR3
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800287#define CONFIG_SYS_SPD_BUS_NUM 0
288#define SPD_EEPROM_ADDRESS 0x51
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800289#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800290#elif defined(CONFIG_T1023RDB)
291#define CONFIG_SYS_FSL_DDR4
292#define CONFIG_SYS_DDR_RAW_TIMING
293#define CONFIG_SYS_SDRAM_SIZE 2048
294#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800295
296/*
297 * IFC Definitions
298 */
299#define CONFIG_SYS_FLASH_BASE 0xe8000000
300#ifdef CONFIG_PHYS_64BIT
301#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
302#else
303#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
304#endif
305
306#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
307#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
308 CSPR_PORT_SIZE_16 | \
309 CSPR_MSEL_NOR | \
310 CSPR_V)
311#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
312
313/* NOR Flash Timing Params */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800314#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800315#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800316#elif defined(CONFIG_T1023RDB)
Shengzhou Liuff7ea2d2015-06-17 16:37:01 +0800317#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800318 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
319#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800320#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
321 FTIM0_NOR_TEADC(0x5) | \
322 FTIM0_NOR_TEAHC(0x5))
323#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
324 FTIM1_NOR_TRAD_NOR(0x1A) |\
325 FTIM1_NOR_TSEQRAD_NOR(0x13))
326#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
327 FTIM2_NOR_TCH(0x4) | \
328 FTIM2_NOR_TWPH(0x0E) | \
329 FTIM2_NOR_TWP(0x1c))
330#define CONFIG_SYS_NOR_FTIM3 0x0
331
332#define CONFIG_SYS_FLASH_QUIET_TEST
333#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
334
335#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
336#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
337#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
338#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
339
340#define CONFIG_SYS_FLASH_EMPTY_INFO
341#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
342
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800343#ifdef CONFIG_T1024RDB
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800344/* CPLD on IFC */
345#define CONFIG_SYS_CPLD_BASE 0xffdf0000
346#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
347#define CONFIG_SYS_CSPR2_EXT (0xf)
348#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
349 | CSPR_PORT_SIZE_8 \
350 | CSPR_MSEL_GPCM \
351 | CSPR_V)
352#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
353#define CONFIG_SYS_CSOR2 0x0
354
355/* CPLD Timing parameters for IFC CS2 */
356#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
357 FTIM0_GPCM_TEADC(0x0e) | \
358 FTIM0_GPCM_TEAHC(0x0e))
359#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
360 FTIM1_GPCM_TRAD(0x1f))
361#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
362 FTIM2_GPCM_TCH(0x8) | \
363 FTIM2_GPCM_TWP(0x1f))
364#define CONFIG_SYS_CS2_FTIM3 0x0
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800365#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800366
367/* NAND Flash on IFC */
368#define CONFIG_NAND_FSL_IFC
369#define CONFIG_SYS_NAND_BASE 0xff800000
370#ifdef CONFIG_PHYS_64BIT
371#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
372#else
373#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
374#endif
375#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
376#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
377 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
378 | CSPR_MSEL_NAND /* MSEL = NAND */ \
379 | CSPR_V)
380#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
381
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800382#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800383#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
384 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
385 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
386 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
387 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
388 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
389 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800390#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
391#elif defined(CONFIG_T1023RDB)
Jaiprakash Singh78429502015-05-22 15:21:07 +0530392#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
393 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
394 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800395 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
396 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
397 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
398 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
399#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
400#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800401
402#define CONFIG_SYS_NAND_ONFI_DETECTION
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800403/* ONFI NAND Flash mode0 Timing Params */
404#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
405 FTIM0_NAND_TWP(0x18) | \
406 FTIM0_NAND_TWCHT(0x07) | \
407 FTIM0_NAND_TWH(0x0a))
408#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
409 FTIM1_NAND_TWBE(0x39) | \
410 FTIM1_NAND_TRR(0x0e) | \
411 FTIM1_NAND_TRP(0x18))
412#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
413 FTIM2_NAND_TREH(0x0a) | \
414 FTIM2_NAND_TWHRE(0x1e))
415#define CONFIG_SYS_NAND_FTIM3 0x0
416
417#define CONFIG_SYS_NAND_DDR_LAW 11
418#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
419#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800420#define CONFIG_CMD_NAND
421
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800422#if defined(CONFIG_NAND)
423#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
424#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
425#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
426#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
427#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
428#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
429#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
430#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
431#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
432#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
433#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
434#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
435#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
436#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
437#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
438#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
439#else
440#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
441#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
442#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
443#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
444#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
445#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
446#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
447#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
448#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
449#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
450#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
451#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
452#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
453#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
454#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
455#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
456#endif
457
458#ifdef CONFIG_SPL_BUILD
459#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
460#else
461#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
462#endif
463
464#if defined(CONFIG_RAMBOOT_PBL)
465#define CONFIG_SYS_RAMBOOT
466#endif
467
468#define CONFIG_BOARD_EARLY_INIT_R
469#define CONFIG_MISC_INIT_R
470
471#define CONFIG_HWCONFIG
472
473/* define to use L1 as initial stack */
474#define CONFIG_L1_INIT_RAM
475#define CONFIG_SYS_INIT_RAM_LOCK
476#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
477#ifdef CONFIG_PHYS_64BIT
478#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700479#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800480/* The assembler doesn't like typecast */
481#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
482 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
483 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
484#else
York Sunb3142e22015-08-17 13:31:51 -0700485#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800486#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
487#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
488#endif
489#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
490
491#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
492 GENERATED_GBL_DATA_SIZE)
493#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
494
495#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
496#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
497
498/* Serial Port */
499#define CONFIG_CONS_INDEX 1
500#define CONFIG_SYS_NS16550
501#define CONFIG_SYS_NS16550_SERIAL
502#define CONFIG_SYS_NS16550_REG_SIZE 1
503#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
504
505#define CONFIG_SYS_BAUDRATE_TABLE \
506 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
507
508#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
509#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
510#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
511#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
512#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
513
514/* Use the HUSH parser */
515#define CONFIG_SYS_HUSH_PARSER
516#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
517
518/* Video */
519#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
520#ifdef CONFIG_FSL_DIU_FB
521#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
522#define CONFIG_VIDEO
523#define CONFIG_CMD_BMP
524#define CONFIG_CFB_CONSOLE
525#define CONFIG_VIDEO_SW_CURSOR
526#define CONFIG_VGA_AS_SINGLE_DEVICE
527#define CONFIG_VIDEO_LOGO
528#define CONFIG_VIDEO_BMP_LOGO
529#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
530/*
531 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
532 * disable empty flash sector detection, which is I/O-intensive.
533 */
534#undef CONFIG_SYS_FLASH_EMPTY_INFO
535#endif
536
537/* pass open firmware flat tree */
538#define CONFIG_OF_LIBFDT
539#define CONFIG_OF_BOARD_SETUP
540#define CONFIG_OF_STDOUT_VIA_ALIAS
541
542/* new uImage format support */
543#define CONFIG_FIT
544#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
545
546/* I2C */
547#define CONFIG_SYS_I2C
548#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
549#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
550#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
551#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
552#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
553#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
554#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
555
Shengzhou Liuff7ea2d2015-06-17 16:37:01 +0800556#define I2C_PCA6408_BUS_NUM 1
557#define I2C_PCA6408_ADDR 0x20
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800558
559/* I2C bus multiplexer */
560#define I2C_MUX_CH_DEFAULT 0x8
561
562/*
563 * RTC configuration
564 */
565#define RTC
566#define CONFIG_RTC_DS1337 1
567#define CONFIG_SYS_I2C_RTC_ADDR 0x68
568
569/*
570 * eSPI - Enhanced SPI
571 */
572#define CONFIG_FSL_ESPI
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800573#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800574#define CONFIG_SPI_FLASH_STMICRO
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800575#elif defined(CONFIG_T1023RDB)
576#define CONFIG_SPI_FLASH_SPANSION
577#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800578#define CONFIG_CMD_SF
579#define CONFIG_SPI_FLASH_BAR
580#define CONFIG_SF_DEFAULT_SPEED 10000000
581#define CONFIG_SF_DEFAULT_MODE 0
582
583/*
584 * General PCIe
585 * Memory space is mapped 1-1, but I/O space must start from 0.
586 */
587#define CONFIG_PCI /* Enable PCI/PCIE */
588#define CONFIG_PCIE1 /* PCIE controler 1 */
589#define CONFIG_PCIE2 /* PCIE controler 2 */
590#define CONFIG_PCIE3 /* PCIE controler 3 */
591#ifdef CONFIG_PPC_T1040
592#define CONFIG_PCIE4 /* PCIE controler 4 */
593#endif
594#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
595#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
596#define CONFIG_PCI_INDIRECT_BRIDGE
597
598#ifdef CONFIG_PCI
599/* controller 1, direct to uli, tgtid 3, Base address 20000 */
600#ifdef CONFIG_PCIE1
601#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
602#ifdef CONFIG_PHYS_64BIT
603#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
604#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
605#else
606#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
607#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
608#endif
609#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
610#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
611#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
612#ifdef CONFIG_PHYS_64BIT
613#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
614#else
615#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
616#endif
617#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
618#endif
619
620/* controller 2, Slot 2, tgtid 2, Base address 201000 */
621#ifdef CONFIG_PCIE2
622#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
623#ifdef CONFIG_PHYS_64BIT
624#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
625#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
626#else
627#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
628#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
629#endif
630#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
631#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
632#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
633#ifdef CONFIG_PHYS_64BIT
634#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
635#else
636#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
637#endif
638#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
639#endif
640
641/* controller 3, Slot 1, tgtid 1, Base address 202000 */
642#ifdef CONFIG_PCIE3
643#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
644#ifdef CONFIG_PHYS_64BIT
645#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
646#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
647#else
648#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
649#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
650#endif
651#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
652#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
653#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
654#ifdef CONFIG_PHYS_64BIT
655#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
656#else
657#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
658#endif
659#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
660#endif
661
662/* controller 4, Base address 203000, to be removed */
663#ifdef CONFIG_PCIE4
664#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
665#ifdef CONFIG_PHYS_64BIT
666#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
667#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
668#else
669#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
670#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
671#endif
672#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
673#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
674#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
675#ifdef CONFIG_PHYS_64BIT
676#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
677#else
678#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
679#endif
680#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
681#endif
682
683#define CONFIG_PCI_PNP /* do pci plug-and-play */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800684#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
685#define CONFIG_DOS_PARTITION
686#endif /* CONFIG_PCI */
687
688/*
689 * USB
690 */
691#define CONFIG_HAS_FSL_DR_USB
692
693#ifdef CONFIG_HAS_FSL_DR_USB
694#define CONFIG_USB_EHCI
695#define CONFIG_CMD_USB
696#define CONFIG_USB_STORAGE
697#define CONFIG_USB_EHCI_FSL
698#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
699#define CONFIG_CMD_EXT2
700#endif
701
702/*
703 * SDHC
704 */
705#define CONFIG_MMC
706#ifdef CONFIG_MMC
707#define CONFIG_FSL_ESDHC
708#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
709#define CONFIG_CMD_MMC
710#define CONFIG_GENERIC_MMC
711#define CONFIG_CMD_EXT2
712#define CONFIG_CMD_FAT
713#define CONFIG_DOS_PARTITION
714#endif
715
716/* Qman/Bman */
717#ifndef CONFIG_NOBQFMAN
718#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500719#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800720#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
721#ifdef CONFIG_PHYS_64BIT
722#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
723#else
724#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
725#endif
726#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500727#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
728#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
729#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
730#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
731#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
732 CONFIG_SYS_BMAN_CENA_SIZE)
733#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
734#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500735#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800736#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
737#ifdef CONFIG_PHYS_64BIT
738#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
739#else
740#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
741#endif
742#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500743#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
744#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
745#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
746#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
747#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
748 CONFIG_SYS_QMAN_CENA_SIZE)
749#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
750#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800751
752#define CONFIG_SYS_DPAA_FMAN
753
Shengzhou Liuff7ea2d2015-06-17 16:37:01 +0800754#ifdef CONFIG_T1024RDB
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800755#define CONFIG_QE
756#define CONFIG_U_QE
Shengzhou Liuff7ea2d2015-06-17 16:37:01 +0800757#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800758/* Default address of microcode for the Linux FMan driver */
759#if defined(CONFIG_SPIFLASH)
760/*
761 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
762 * env, so we got 0x110000.
763 */
764#define CONFIG_SYS_QE_FW_IN_SPIFLASH
765#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
766#define CONFIG_SYS_QE_FW_ADDR 0x130000
767#elif defined(CONFIG_SDCARD)
768/*
769 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
770 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
771 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
772 */
773#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
774#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
775#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
776#elif defined(CONFIG_NAND)
777#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800778#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800779#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
780#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800781#elif defined(CONFIG_T1023RDB)
782#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
783#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
784#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800785#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
786/*
787 * Slave has no ucode locally, it can fetch this from remote. When implementing
788 * in two corenet boards, slave's ucode could be stored in master's memory
789 * space, the address can be mapped from slave TLB->slave LAW->
790 * slave SRIO or PCIE outbound window->master inbound window->
791 * master LAW->the ucode address in master's memory space.
792 */
793#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
794#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
795#else
796#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
797#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
798#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
799#endif
800#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
801#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
802#endif /* CONFIG_NOBQFMAN */
803
804#ifdef CONFIG_SYS_DPAA_FMAN
805#define CONFIG_FMAN_ENET
806#define CONFIG_PHYLIB_10G
807#define CONFIG_PHY_REALTEK
Shengzhou Liue26416a2014-12-17 16:51:08 +0800808#define CONFIG_PHY_AQUANTIA
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800809#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800810#define RGMII_PHY1_ADDR 0x2
811#define RGMII_PHY2_ADDR 0x6
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800812#define SGMII_AQR_PHY_ADDR 0x2
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800813#define FM1_10GEC1_PHY_ADDR 0x1
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800814#elif defined(CONFIG_T1023RDB)
815#define RGMII_PHY1_ADDR 0x1
816#define SGMII_RTK_PHY_ADDR 0x3
817#define SGMII_AQR_PHY_ADDR 0x2
818#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800819#endif
820
821#ifdef CONFIG_FMAN_ENET
822#define CONFIG_MII /* MII PHY management */
823#define CONFIG_ETHPRIME "FM1@DTSEC4"
824#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
825#endif
826
827/*
828 * Dynamic MTD Partition support with mtdparts
829 */
830#ifndef CONFIG_SYS_NO_FLASH
831#define CONFIG_MTD_DEVICE
832#define CONFIG_MTD_PARTITIONS
833#define CONFIG_CMD_MTDPARTS
834#define CONFIG_FLASH_CFI_MTD
835#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
836 "spi0=spife110000.1"
837#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
838 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
839 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
840 "1m(uboot),5m(kernel),128k(dtb),-(user)"
841#endif
842
843/*
844 * Environment
845 */
846#define CONFIG_LOADS_ECHO /* echo on for serial download */
847#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
848
849/*
850 * Command line configuration.
851 */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800852#define CONFIG_CMD_DATE
853#define CONFIG_CMD_DHCP
854#define CONFIG_CMD_EEPROM
855#define CONFIG_CMD_ELF
856#define CONFIG_CMD_ERRATA
857#define CONFIG_CMD_GREPENV
858#define CONFIG_CMD_IRQ
859#define CONFIG_CMD_I2C
860#define CONFIG_CMD_MII
861#define CONFIG_CMD_PING
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800862#define CONFIG_CMD_REGINFO
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800863
864#ifdef CONFIG_PCI
865#define CONFIG_CMD_PCI
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800866#endif
867
868/*
869 * Miscellaneous configurable options
870 */
871#define CONFIG_SYS_LONGHELP /* undef to save memory */
872#define CONFIG_CMDLINE_EDITING /* Command-line editing */
873#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
874#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800875#ifdef CONFIG_CMD_KGDB
876#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
877#else
878#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
879#endif
880#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
881#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
882#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
883
884/*
885 * For booting Linux, the board info and command line data
886 * have to be in the first 64 MB of memory, since this is
887 * the maximum mapped by the Linux kernel during initialization.
888 */
889#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
890#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
891
892#ifdef CONFIG_CMD_KGDB
893#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
894#endif
895
896/*
897 * Environment Configuration
898 */
899#define CONFIG_ROOTPATH "/opt/nfsroot"
900#define CONFIG_BOOTFILE "uImage"
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800901#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800902#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
903#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
904#define CONFIG_BAUDRATE 115200
905#define __USB_PHY_TYPE utmi
906
907#ifdef CONFIG_PPC_T1024
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800908#define CONFIG_BOARDNAME t1024rdb
909#define BANK_INTLV cs0_cs1
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800910#else
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800911#define CONFIG_BOARDNAME t1023rdb
912#define BANK_INTLV null
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800913#endif
914
915#define CONFIG_EXTRA_ENV_SETTINGS \
916 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800917 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800918 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
919 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
920 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
921 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
922 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
923 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
924 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
925 "netdev=eth0\0" \
926 "tftpflash=tftpboot $loadaddr $uboot && " \
927 "protect off $ubootaddr +$filesize && " \
928 "erase $ubootaddr +$filesize && " \
929 "cp.b $loadaddr $ubootaddr $filesize && " \
930 "protect on $ubootaddr +$filesize && " \
931 "cmp.b $loadaddr $ubootaddr $filesize\0" \
932 "consoledev=ttyS0\0" \
933 "ramdiskaddr=2000000\0" \
934 "fdtaddr=c00000\0" \
935 "bdev=sda3\0"
936
937#define CONFIG_LINUX \
938 "setenv bootargs root=/dev/ram rw " \
939 "console=$consoledev,$baudrate $othbootargs;" \
940 "setenv ramdiskaddr 0x02000000;" \
941 "setenv fdtaddr 0x00c00000;" \
942 "setenv loadaddr 0x1000000;" \
943 "bootm $loadaddr $ramdiskaddr $fdtaddr"
944
945
946#define CONFIG_NFSBOOTCOMMAND \
947 "setenv bootargs root=/dev/nfs rw " \
948 "nfsroot=$serverip:$rootpath " \
949 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
950 "console=$consoledev,$baudrate $othbootargs;" \
951 "tftp $loadaddr $bootfile;" \
952 "tftp $fdtaddr $fdtfile;" \
953 "bootm $loadaddr - $fdtaddr"
954
955#define CONFIG_BOOTCOMMAND CONFIG_LINUX
956
957#ifdef CONFIG_SECURE_BOOT
958#include <asm/fsl_secure_boot.h>
959#endif
960
961#endif /* __T1024RDB_H */