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gerrit.cesnet.cz / github / trini / u-boot / 155fd766573981090e638b493d5857562151862e / . / include / asm-blackfin / arch-bf533 / cplbtab.h
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Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]1/*This file is subject to the terms and conditions of the GNU General Public
2 * License.
3 *
4 * Blackfin BF533/2.6 support : LG Soft India
5 * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
6 * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
7 * shouldn't be victimized. cplbmgr.S search logic is corrected
8 * to findout the appropriate victim.
9 * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
10 * : LG Soft India
11 */
12#include <config.h>
13
14#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
15#define __ARCH_BFINNOMMU_CPLBTAB_H
16
17/*************************************************************************
18 * ICPLB TABLE
19 *************************************************************************/
20
21.data
22/* This table is configurable */
23 .align 4;
24
25/* Data Attibutes*/
26
27#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
28#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
29#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
30#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
31
32/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
33
34#define ANOMALY_05000158 0x200
35#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
36#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
37#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
38#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
39#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
40#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
41
42#else /*Write Through */
43#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
44#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
45#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
46#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
47#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
48#endif
49
50.align 4;
51.global _ipdt_table _ipdt_table:.byte4 0x00000000;
52.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
53.byte4 0x00400000;
54.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
55.byte4 0x00800000;
56.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
57.byte4 0x00C00000;
58.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
59.byte4 0x01000000;
60.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
61.byte4 0x01400000;
62.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
63.byte4 0x01800000;
64.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
65.byte4 0x01C00000;
66.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
67#ifndef CONFIG_EZKIT /*STAMP Memory regions */
68.byte4 0x02000000;
69.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
70.byte4 0x02400000;
71.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
72.byte4 0x02800000;
73.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
74.byte4 0x02C00000;
75.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
76.byte4 0x03000000;
77.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
78.byte4 0x03400000;
79.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
80.byte4 0x03800000;
81.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
82.byte4 0x03C00000;
83.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
84#endif
85.byte4 0x20000000;
86.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
87
88#ifdef CONFIG_STAMP
89.byte4 0x04000000;
90.byte4(SDRAM_IGENERIC);
91.byte4 0x04400000;
92.byte4(SDRAM_IGENERIC);
93.byte4 0x04800000;
94.byte4(SDRAM_IGENERIC);
95.byte4 0x04C00000;
96.byte4(SDRAM_IGENERIC);
97.byte4 0x05000000;
98.byte4(SDRAM_IGENERIC);
99.byte4 0x05400000;
100.byte4(SDRAM_IGENERIC);
101.byte4 0x05800000;
102.byte4(SDRAM_IGENERIC);
103.byte4 0x05C00000;
104.byte4(SDRAM_IGENERIC);
105.byte4 0x06000000;
106.byte4(SDRAM_IGENERIC); /*SDRAM_Page25 */
107.byte4 0x06400000;
108.byte4(SDRAM_IGENERIC); /*SDRAM_Page26 */
109.byte4 0x06800000;
110.byte4(SDRAM_IGENERIC); /*SDRAM_Page27 */
111.byte4 0x06C00000;
112.byte4(SDRAM_IGENERIC); /*SDRAM_Page28 */
113.byte4 0x07000000;
114.byte4(SDRAM_IGENERIC); /*SDRAM_Page29 */
115.byte4 0x07400000;
116.byte4(SDRAM_IGENERIC); /*SDRAM_Page30 */
117.byte4 0x07800000;
118.byte4(SDRAM_IGENERIC); /*SDRAM_Page31 */
119.byte4 0x07C00000;
120.byte4(SDRAM_IKERNEL); /*SDRAM_Page32 */
121#endif
122.byte4 0xffffffff; /* end of section - termination */
123
124/**********************************************************************
125 * PAGE DESCRIPTOR TABLE
126 *
127 **********************************************************************/
128
129/* Till here we are discussing about the static memory management model.
130 * However, the operating envoronments commonly define more CPLB
131 * descriptors to cover the entire addressable memory than will fit into
132 * the available on-chip 16 CPLB MMRs. When this happens, the below table
133 * will be used which will hold all the potentially required CPLB descriptors
134 *
135 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
136 */
137.global _dpdt_table _dpdt_table:.byte4 0x00000000;
138.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
139.byte4 0x00400000;
140.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
141.byte4 0x00800000;
142.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
143.byte4 0x00C00000;
144.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
145.byte4 0x01000000;
146.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
147.byte4 0x01400000;
148.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
149.byte4 0x01800000;
150.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
151.byte4 0x01C00000;
152.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
153
154#ifndef CONFIG_EZKIT
155.byte4 0x02000000;
156.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
157.byte4 0x02400000;
158.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
159.byte4 0x02800000;
160.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
161.byte4 0x02C00000;
162.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
163.byte4 0x03000000;
164.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
165.byte4 0x03400000;
166.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
167.byte4 0x03800000;
168.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
169.byte4 0x03C00000;
170.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
171#endif
172
173#ifdef CONFIG_STAMP
174.byte4 0x04000000;
175.byte4(SDRAM_DGENERIC);
176.byte4 0x04400000;
177.byte4(SDRAM_DGENERIC);
178.byte4 0x04800000;
179.byte4(SDRAM_DGENERIC);
180.byte4 0x04C00000;
181.byte4(SDRAM_DGENERIC);
182.byte4 0x05000000;
183.byte4(SDRAM_DGENERIC);
184.byte4 0x05400000;
185.byte4(SDRAM_DGENERIC);
186.byte4 0x05800000;
187.byte4(SDRAM_DGENERIC);
188.byte4 0x05C00000;
189.byte4(SDRAM_DGENERIC);
190.byte4 0x06000000;
191.byte4(SDRAM_DGENERIC); /*SDRAM_Page25 */
192.byte4 0x06400000;
193.byte4(SDRAM_DGENERIC); /*SDRAM_Page26 */
194.byte4 0x06800000;
195.byte4(SDRAM_DGENERIC); /*SDRAM_Page27 */
196.byte4 0x06C00000;
197.byte4(SDRAM_DGENERIC); /*SDRAM_Page28 */
198.byte4 0x07000000;
199.byte4(SDRAM_DGENERIC); /*SDRAM_Page29 */
200.byte4 0x07400000;
201.byte4(SDRAM_DGENERIC); /*SDRAM_Page30 */
202.byte4 0x07800000;
203.byte4(SDRAM_DGENERIC); /*SDRAM_Page31 */
204.byte4 0x07C00000;
205.byte4(SDRAM_DKERNEL); /*SDRAM_Page32 */
206#endif
207
208.byte4 0x20000000;
209.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
210
211#if (BFIN_CPU == ADSP_BF533)
212.byte4 0xFF800000;
213.byte4(L1_DMEMORY);
214.byte4 0xFF801000;
215.byte4(L1_DMEMORY);
216.byte4 0xFF802000;
217.byte4(L1_DMEMORY);
218.byte4 0xFF803000;
219.byte4(L1_DMEMORY);
220#endif
221.byte4 0xFF804000;
222.byte4(L1_DMEMORY);
223.byte4 0xFF805000;
224.byte4(L1_DMEMORY);
225.byte4 0xFF806000;
226.byte4(L1_DMEMORY);
227.byte4 0xFF807000;
228.byte4(L1_DMEMORY);
229#if (BFIN_CPU == ADSP_BF533)
230.byte4 0xFF900000;
231.byte4(L1_DMEMORY);
232.byte4 0xFF901000;
233.byte4(L1_DMEMORY);
234.byte4 0xFF902000;
235.byte4(L1_DMEMORY);
236.byte4 0xFF903000;
237.byte4(L1_DMEMORY);
238#endif
239#if ((BFIN_CPU == ADSP_BF532) || (BFIN_CPU == ADSP_BF533))
240.byte4 0xFF904000;
241.byte4(L1_DMEMORY);
242.byte4 0xFF905000;
243.byte4(L1_DMEMORY);
244.byte4 0xFF906000;
245.byte4(L1_DMEMORY);
246.byte4 0xFF907000;
247.byte4(L1_DMEMORY);
248#endif
249.byte4 0xFFB00000;
250.byte4(L1_DMEMORY);
251
252.byte4 0xffffffff; /*end of section - termination */
253
254#ifdef CONFIG_CPLB_INFO
255.global _ipdt_swapcount_table; /* swapin count first, then swapout count */
256_ipdt_swapcount_table:
257.byte4 0x00000000;
258.byte4 0x00000000;
259.byte4 0x00000000;
260.byte4 0x00000000;
261.byte4 0x00000000;
262.byte4 0x00000000;
263.byte4 0x00000000;
264.byte4 0x00000000;
265.byte4 0x00000000;
266.byte4 0x00000000; /* 10 */
267.byte4 0x00000000;
268.byte4 0x00000000;
269.byte4 0x00000000;
270.byte4 0x00000000;
271.byte4 0x00000000;
272.byte4 0x00000000;
273.byte4 0x00000000;
274.byte4 0x00000000;
275.byte4 0x00000000;
276.byte4 0x00000000; /* 20 */
277.byte4 0x00000000;
278.byte4 0x00000000;
279.byte4 0x00000000;
280.byte4 0x00000000;
281.byte4 0x00000000;
282.byte4 0x00000000;
283.byte4 0x00000000;
284.byte4 0x00000000;
285.byte4 0x00000000;
286.byte4 0x00000000; /* 30 */
287.byte4 0x00000000;
288.byte4 0x00000000;
289.byte4 0x00000000;
290.byte4 0x00000000;
291.byte4 0x00000000;
292.byte4 0x00000000;
293.byte4 0x00000000;
294.byte4 0x00000000;
295.byte4 0x00000000;
296.byte4 0x00000000; /* 40 */
297.byte4 0x00000000;
298.byte4 0x00000000;
299.byte4 0x00000000;
300.byte4 0x00000000;
301.byte4 0x00000000;
302.byte4 0x00000000;
303.byte4 0x00000000;
304.byte4 0x00000000;
305.byte4 0x00000000;
306.byte4 0x00000000; /* 50 */
307.byte4 0x00000000;
308.byte4 0x00000000;
309.byte4 0x00000000;
310.byte4 0x00000000;
311.byte4 0x00000000;
312.byte4 0x00000000;
313.byte4 0x00000000;
314.byte4 0x00000000;
315.byte4 0x00000000;
316.byte4 0x00000000; /* 60 */
317.byte4 0x00000000;
318.byte4 0x00000000;
319.byte4 0x00000000;
320.byte4 0x00000000;
321.byte4 0x00000000;
322.byte4 0x00000000;
323.byte4 0x00000000;
324.byte4 0x00000000;
325.byte4 0x00000000;
326.byte4 0x00000000; /* 70 */
327.byte4 0x00000000;
328.byte4 0x00000000;
329.byte4 0x00000000;
330.byte4 0x00000000;
331.byte4 0x00000000;
332.byte4 0x00000000;
333.byte4 0x00000000;
334.byte4 0x00000000;
335.byte4 0x00000000;
336.byte4 0x00000000; /* 80 */
337.byte4 0x00000000;
338.byte4 0x00000000;
339.byte4 0x00000000;
340.byte4 0x00000000;
341.byte4 0x00000000;
342.byte4 0x00000000;
343.byte4 0x00000000;
344.byte4 0x00000000;
345.byte4 0x00000000;
346.byte4 0x00000000; /* 90 */
347.byte4 0x00000000;
348.byte4 0x00000000;
349.byte4 0x00000000;
350.byte4 0x00000000;
351.byte4 0x00000000;
352.byte4 0x00000000;
353.byte4 0x00000000;
354.byte4 0x00000000;
355.byte4 0x00000000;
356.byte4 0x00000000; /* 100 */
357
358.global _dpdt_swapcount_table; /* swapin count first, then swapout count */
359_dpdt_swapcount_table:
360.byte4 0x00000000;
361.byte4 0x00000000;
362.byte4 0x00000000;
363.byte4 0x00000000;
364.byte4 0x00000000;
365.byte4 0x00000000;
366.byte4 0x00000000;
367.byte4 0x00000000;
368.byte4 0x00000000;
369.byte4 0x00000000; /* 10 */
370.byte4 0x00000000;
371.byte4 0x00000000;
372.byte4 0x00000000;
373.byte4 0x00000000;
374.byte4 0x00000000;
375.byte4 0x00000000;
376.byte4 0x00000000;
377.byte4 0x00000000;
378.byte4 0x00000000;
379.byte4 0x00000000; /* 20 */
380.byte4 0x00000000;
381.byte4 0x00000000;
382.byte4 0x00000000;
383.byte4 0x00000000;
384.byte4 0x00000000;
385.byte4 0x00000000;
386.byte4 0x00000000;
387.byte4 0x00000000;
388.byte4 0x00000000;
389.byte4 0x00000000; /* 30 */
390.byte4 0x00000000;
391.byte4 0x00000000;
392.byte4 0x00000000;
393.byte4 0x00000000;
394.byte4 0x00000000;
395.byte4 0x00000000;
396.byte4 0x00000000;
397.byte4 0x00000000;
398.byte4 0x00000000;
399.byte4 0x00000000; /* 40 */
400.byte4 0x00000000;
401.byte4 0x00000000;
402.byte4 0x00000000;
403.byte4 0x00000000;
404.byte4 0x00000000;
405.byte4 0x00000000;
406.byte4 0x00000000;
407.byte4 0x00000000;
408.byte4 0x00000000;
409.byte4 0x00000000; /* 50 */
410.byte4 0x00000000;
411.byte4 0x00000000;
412.byte4 0x00000000;
413.byte4 0x00000000;
414.byte4 0x00000000;
415.byte4 0x00000000;
416.byte4 0x00000000;
417.byte4 0x00000000;
418.byte4 0x00000000;
419.byte4 0x00000000; /* 60 */
420.byte4 0x00000000;
421.byte4 0x00000000;
422.byte4 0x00000000;
423.byte4 0x00000000;
424.byte4 0x00000000;
425.byte4 0x00000000;
426.byte4 0x00000000;
427.byte4 0x00000000;
428.byte4 0x00000000;
429.byte4 0x00000000; /* 70 */
430.byte4 0x00000000;
431.byte4 0x00000000;
432.byte4 0x00000000;
433.byte4 0x00000000;
434.byte4 0x00000000;
435.byte4 0x00000000;
436.byte4 0x00000000;
437.byte4 0x00000000;
438.byte4 0x00000000;
439.byte4 0x00000000; /* 80 */
440.byte4 0x00000000;
441.byte4 0x00000000;
442.byte4 0x00000000;
443.byte4 0x00000000;
444.byte4 0x00000000;
445.byte4 0x00000000;
446.byte4 0x00000000;
447.byte4 0x00000000;
448.byte4 0x00000000;
449.byte4 0x00000000; /* 80 */
450.byte4 0x00000000;
451.byte4 0x00000000;
452.byte4 0x00000000;
453.byte4 0x00000000;
454.byte4 0x00000000;
455.byte4 0x00000000;
456.byte4 0x00000000;
457.byte4 0x00000000;
458.byte4 0x00000000;
459.byte4 0x00000000; /* 100 */
460.byte4 0x00000000;
461.byte4 0x00000000;
462.byte4 0x00000000;
463.byte4 0x00000000;
464.byte4 0x00000000;
465.byte4 0x00000000;
466.byte4 0x00000000;
467.byte4 0x00000000;
468.byte4 0x00000000;
469.byte4 0x00000000; /* 110 */
470.byte4 0x00000000;
471.byte4 0x00000000;
472.byte4 0x00000000;
473.byte4 0x00000000;
474.byte4 0x00000000;
475.byte4 0x00000000;
476.byte4 0x00000000;
477.byte4 0x00000000;
478.byte4 0x00000000;
479.byte4 0x00000000; /* 120 */
480#endif
481
482#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/