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Marek Vasut71a758e12011-11-08 23:18:09 +00001/*
2 * Freescale i.MX28 SSP MMC driver
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
9 * Terry Lv
10 *
11 * Copyright 2007, Freescale Semiconductor, Inc
12 * Andy Fleming
13 *
14 * Based vaguely on the pxa mmc code:
15 * (C) Copyright 2003
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
17 *
18 * See file CREDITS for list of people who contributed to this
19 * project.
20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * MA 02111-1307 USA
35 */
36#include <common.h>
37#include <malloc.h>
38#include <mmc.h>
39#include <asm/errno.h>
40#include <asm/io.h>
41#include <asm/arch/clock.h>
42#include <asm/arch/imx-regs.h>
43#include <asm/arch/sys_proto.h>
Marek Vasut3687c412012-03-15 18:33:21 +000044#include <asm/arch/dma.h>
Marek Vasut4e6d81d2012-08-26 15:19:07 +000045#include <bouncebuf.h>
Marek Vasut71a758e12011-11-08 23:18:09 +000046
47struct mxsmmc_priv {
48 int id;
Otavio Salvador9c471142012-08-05 09:05:31 +000049 struct mxs_ssp_regs *regs;
Marek Vasut71a758e12011-11-08 23:18:09 +000050 uint32_t buswidth;
51 int (*mmc_is_wp)(int);
Marek Vasut3687c412012-03-15 18:33:21 +000052 struct mxs_dma_desc *desc;
Marek Vasut71a758e12011-11-08 23:18:09 +000053};
54
55#define MXSMMC_MAX_TIMEOUT 10000
Marek Vasut20255902012-07-06 21:25:56 +000056#define MXSMMC_SMALL_TRANSFER 512
Marek Vasut71a758e12011-11-08 23:18:09 +000057
Marek Vasut86983322012-07-06 21:25:55 +000058static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
59{
60 struct mxs_ssp_regs *ssp_regs = priv->regs;
61 uint32_t *data_ptr;
62 int timeout = MXSMMC_MAX_TIMEOUT;
63 uint32_t reg;
64 uint32_t data_count = data->blocksize * data->blocks;
65
66 if (data->flags & MMC_DATA_READ) {
67 data_ptr = (uint32_t *)data->dest;
68 while (data_count && --timeout) {
69 reg = readl(&ssp_regs->hw_ssp_status);
70 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
71 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
72 data_count -= 4;
73 timeout = MXSMMC_MAX_TIMEOUT;
74 } else
75 udelay(1000);
76 }
77 } else {
78 data_ptr = (uint32_t *)data->src;
79 timeout *= 100;
80 while (data_count && --timeout) {
81 reg = readl(&ssp_regs->hw_ssp_status);
82 if (!(reg & SSP_STATUS_FIFO_FULL)) {
83 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
84 data_count -= 4;
85 timeout = MXSMMC_MAX_TIMEOUT;
86 } else
87 udelay(1000);
88 }
89 }
90
91 return timeout ? 0 : COMM_ERR;
92}
Marek Vasut20255902012-07-06 21:25:56 +000093
Marek Vasut86983322012-07-06 21:25:55 +000094static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
95{
96 uint32_t data_count = data->blocksize * data->blocks;
Marek Vasut86983322012-07-06 21:25:55 +000097 int dmach;
Marek Vasutabb85be2012-07-06 21:25:57 +000098 struct mxs_dma_desc *desc = priv->desc;
Stephen Warren84d35b22012-11-06 11:27:29 +000099 void *addr;
100 unsigned int flags;
101 struct bounce_buffer bbstate;
Marek Vasutabb85be2012-07-06 21:25:57 +0000102
103 memset(desc, 0, sizeof(struct mxs_dma_desc));
104 desc->address = (dma_addr_t)desc;
Marek Vasut86983322012-07-06 21:25:55 +0000105
Marek Vasut86983322012-07-06 21:25:55 +0000106 if (data->flags & MMC_DATA_READ) {
107 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000108 addr = data->dest;
109 flags = GEN_BB_WRITE;
Marek Vasut86983322012-07-06 21:25:55 +0000110 } else {
111 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000112 addr = (void *)data->src;
113 flags = GEN_BB_READ;
114 }
Marek Vasut86983322012-07-06 21:25:55 +0000115
Stephen Warren84d35b22012-11-06 11:27:29 +0000116 bounce_buffer_start(&bbstate, addr, data_count, flags);
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000117
Stephen Warren84d35b22012-11-06 11:27:29 +0000118 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
Marek Vasut97ed12c2012-08-31 16:18:10 +0000119
Marek Vasut86983322012-07-06 21:25:55 +0000120 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
121 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
122
Marek Vasut86983322012-07-06 21:25:55 +0000123 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
124 mxs_dma_desc_append(dmach, priv->desc);
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000125 if (mxs_dma_go(dmach)) {
Stephen Warren84d35b22012-11-06 11:27:29 +0000126 bounce_buffer_stop(&bbstate);
Marek Vasut86983322012-07-06 21:25:55 +0000127 return COMM_ERR;
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000128 }
Marek Vasut86983322012-07-06 21:25:55 +0000129
Stephen Warren84d35b22012-11-06 11:27:29 +0000130 bounce_buffer_stop(&bbstate);
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000131
Marek Vasut86983322012-07-06 21:25:55 +0000132 return 0;
133}
Marek Vasut86983322012-07-06 21:25:55 +0000134
Marek Vasut71a758e12011-11-08 23:18:09 +0000135/*
136 * Sends a command out on the bus. Takes the mmc pointer,
137 * a command pointer, and an optional data pointer.
138 */
139static int
140mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
141{
142 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
Otavio Salvador9c471142012-08-05 09:05:31 +0000143 struct mxs_ssp_regs *ssp_regs = priv->regs;
Marek Vasut71a758e12011-11-08 23:18:09 +0000144 uint32_t reg;
145 int timeout;
Marek Vasut71a758e12011-11-08 23:18:09 +0000146 uint32_t ctrl0;
Marek Vasut86983322012-07-06 21:25:55 +0000147 int ret;
Marek Vasut71a758e12011-11-08 23:18:09 +0000148
149 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
150
151 /* Check bus busy */
152 timeout = MXSMMC_MAX_TIMEOUT;
153 while (--timeout) {
154 udelay(1000);
155 reg = readl(&ssp_regs->hw_ssp_status);
156 if (!(reg &
157 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
158 SSP_STATUS_CMD_BUSY))) {
159 break;
160 }
161 }
162
163 if (!timeout) {
164 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
165 return TIMEOUT;
166 }
167
168 /* See if card is present */
169 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
170 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
171 return NO_CARD_ERR;
172 }
173
174 /* Start building CTRL0 contents */
175 ctrl0 = priv->buswidth;
176
177 /* Set up command */
178 if (!(cmd->resp_type & MMC_RSP_CRC))
179 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
180 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
181 ctrl0 |= SSP_CTRL0_GET_RESP;
182 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
183 ctrl0 |= SSP_CTRL0_LONG_RESP;
184
Marek Vasutabb85be2012-07-06 21:25:57 +0000185 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
186 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
187 else
188 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
189
Marek Vasut71a758e12011-11-08 23:18:09 +0000190 /* Command index */
191 reg = readl(&ssp_regs->hw_ssp_cmd0);
192 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
193 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
194 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
195 reg |= SSP_CMD0_APPEND_8CYC;
196 writel(reg, &ssp_regs->hw_ssp_cmd0);
197
198 /* Command argument */
199 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
200
201 /* Set up data */
202 if (data) {
203 /* READ or WRITE */
204 if (data->flags & MMC_DATA_READ) {
205 ctrl0 |= SSP_CTRL0_READ;
Marek Vasutc7527b72012-05-01 11:09:52 +0000206 } else if (priv->mmc_is_wp &&
207 priv->mmc_is_wp(mmc->block_dev.dev)) {
Marek Vasut71a758e12011-11-08 23:18:09 +0000208 printf("MMC%d: Can not write a locked card!\n",
209 mmc->block_dev.dev);
210 return UNUSABLE_ERR;
211 }
212
213 ctrl0 |= SSP_CTRL0_DATA_XFER;
214 reg = ((data->blocks - 1) <<
215 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
216 ((ffs(data->blocksize) - 1) <<
217 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
218 writel(reg, &ssp_regs->hw_ssp_block_size);
219
220 reg = data->blocksize * data->blocks;
221 writel(reg, &ssp_regs->hw_ssp_xfer_size);
222 }
223
224 /* Kick off the command */
225 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
226 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
227
228 /* Wait for the command to complete */
229 timeout = MXSMMC_MAX_TIMEOUT;
230 while (--timeout) {
231 udelay(1000);
232 reg = readl(&ssp_regs->hw_ssp_status);
233 if (!(reg & SSP_STATUS_CMD_BUSY))
234 break;
235 }
236
237 if (!timeout) {
238 printf("MMC%d: Command %d busy\n",
239 mmc->block_dev.dev, cmd->cmdidx);
240 return TIMEOUT;
241 }
242
243 /* Check command timeout */
244 if (reg & SSP_STATUS_RESP_TIMEOUT) {
245 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
246 mmc->block_dev.dev, cmd->cmdidx, reg);
247 return TIMEOUT;
248 }
249
250 /* Check command errors */
251 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
252 printf("MMC%d: Command %d error (status 0x%08x)!\n",
253 mmc->block_dev.dev, cmd->cmdidx, reg);
254 return COMM_ERR;
255 }
256
257 /* Copy response to response buffer */
258 if (cmd->resp_type & MMC_RSP_136) {
259 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
260 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
261 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
262 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
263 } else
264 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
265
266 /* Return if no data to process */
267 if (!data)
268 return 0;
269
Marek Vasut20255902012-07-06 21:25:56 +0000270 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
Marek Vasut20255902012-07-06 21:25:56 +0000271 ret = mxsmmc_send_cmd_pio(priv, data);
272 if (ret) {
273 printf("MMC%d: Data timeout with command %d "
274 "(status 0x%08x)!\n",
275 mmc->block_dev.dev, cmd->cmdidx, reg);
276 return ret;
277 }
Marek Vasutabb85be2012-07-06 21:25:57 +0000278 } else {
279 ret = mxsmmc_send_cmd_dma(priv, data);
280 if (ret) {
281 printf("MMC%d: DMA transfer failed\n",
282 mmc->block_dev.dev);
283 return ret;
284 }
Marek Vasut4cc76c62012-04-05 03:30:35 +0000285 }
Marek Vasut3687c412012-03-15 18:33:21 +0000286
Marek Vasut71a758e12011-11-08 23:18:09 +0000287 /* Check data errors */
288 reg = readl(&ssp_regs->hw_ssp_status);
289 if (reg &
290 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
291 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
292 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
293 mmc->block_dev.dev, cmd->cmdidx, reg);
294 return COMM_ERR;
295 }
296
297 return 0;
298}
299
300static void mxsmmc_set_ios(struct mmc *mmc)
301{
302 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
Otavio Salvador9c471142012-08-05 09:05:31 +0000303 struct mxs_ssp_regs *ssp_regs = priv->regs;
Marek Vasut71a758e12011-11-08 23:18:09 +0000304
305 /* Set the clock speed */
306 if (mmc->clock)
307 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
308
309 switch (mmc->bus_width) {
310 case 1:
311 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
312 break;
313 case 4:
314 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
315 break;
316 case 8:
317 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
318 break;
319 }
320
321 /* Set the bus width */
322 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
323 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
324
325 debug("MMC%d: Set %d bits bus width\n",
326 mmc->block_dev.dev, mmc->bus_width);
327}
328
329static int mxsmmc_init(struct mmc *mmc)
330{
331 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
Otavio Salvador9c471142012-08-05 09:05:31 +0000332 struct mxs_ssp_regs *ssp_regs = priv->regs;
Marek Vasut71a758e12011-11-08 23:18:09 +0000333
334 /* Reset SSP */
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000335 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
Marek Vasut71a758e12011-11-08 23:18:09 +0000336
337 /* 8 bits word length in MMC mode */
338 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
Marek Vasutabb85be2012-07-06 21:25:57 +0000339 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK |
340 SSP_CTRL1_DMA_ENABLE,
341 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
Marek Vasut71a758e12011-11-08 23:18:09 +0000342
343 /* Set initial bit clock 400 KHz */
344 mx28_set_ssp_busclock(priv->id, 400);
345
346 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
347 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
348 udelay(200);
349 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
350
351 return 0;
352}
353
354int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
355{
Marek Vasut71a758e12011-11-08 23:18:09 +0000356 struct mmc *mmc = NULL;
357 struct mxsmmc_priv *priv = NULL;
Marek Vasut96666a32012-04-08 17:34:46 +0000358 int ret;
Marek Vasut71a758e12011-11-08 23:18:09 +0000359
360 mmc = malloc(sizeof(struct mmc));
361 if (!mmc)
362 return -ENOMEM;
363
364 priv = malloc(sizeof(struct mxsmmc_priv));
365 if (!priv) {
366 free(mmc);
367 return -ENOMEM;
368 }
369
Marek Vasut3687c412012-03-15 18:33:21 +0000370 priv->desc = mxs_dma_desc_alloc();
371 if (!priv->desc) {
372 free(priv);
373 free(mmc);
374 return -ENOMEM;
375 }
376
Marek Vasut96666a32012-04-08 17:34:46 +0000377 ret = mxs_dma_init_channel(id);
378 if (ret)
379 return ret;
380
Marek Vasut71a758e12011-11-08 23:18:09 +0000381 priv->mmc_is_wp = wp;
382 priv->id = id;
Marek Vasut14e26bc2013-01-11 03:19:02 +0000383 priv->regs = mxs_ssp_regs_by_bus(id);
Marek Vasut71a758e12011-11-08 23:18:09 +0000384
385 sprintf(mmc->name, "MXS MMC");
386 mmc->send_cmd = mxsmmc_send_cmd;
387 mmc->set_ios = mxsmmc_set_ios;
388 mmc->init = mxsmmc_init;
Thierry Reding48972d92012-01-02 01:15:37 +0000389 mmc->getcd = NULL;
Marek Vasut71a758e12011-11-08 23:18:09 +0000390 mmc->priv = priv;
391
392 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
393
394 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
395 MMC_MODE_HS_52MHz | MMC_MODE_HS;
396
397 /*
398 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
399 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
400 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
401 * CLOCK_RATE could be any integer from 0 to 255.
402 */
403 mmc->f_min = 400000;
404 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
Marek Vasute7205902012-04-08 18:50:18 +0000405 mmc->b_max = 0x20;
Marek Vasut71a758e12011-11-08 23:18:09 +0000406
407 mmc_register(mmc);
408 return 0;
409}