blob: d0aa5eabe5ef054e01f233263f29294b2552c781 [file] [log] [blame]
Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01002/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01004 */
5
6/ {
7 aliases {
8 gpio0 = &gpioa;
9 gpio1 = &gpiob;
10 gpio2 = &gpioc;
11 gpio3 = &gpiod;
12 gpio4 = &gpioe;
13 gpio5 = &gpiof;
14 gpio6 = &gpiog;
15 gpio7 = &gpioh;
16 gpio8 = &gpioi;
17 gpio9 = &gpioj;
18 gpio10 = &gpiok;
19 gpio25 = &gpioz;
Patrick Delaunay1258e462019-04-12 14:38:28 +020020 pinctrl0 = &pinctrl;
21 pinctrl1 = &pinctrl_z;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010022 };
23
Patrick Delaunay35a54d42019-07-11 11:15:28 +020024 clocks {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010025 u-boot,dm-pre-reloc;
26 };
27
Patrick Delaunay67b76842019-07-30 19:16:15 +020028 /* need PSCI for sysreset during board_f */
29 psci {
30 u-boot,dm-pre-proper;
31 };
32
Patrick Delaunay35a54d42019-07-11 11:15:28 +020033 reboot {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010034 u-boot,dm-pre-reloc;
Patrick Delaunay500327e2020-07-06 13:26:53 +020035 compatible = "syscon-reboot";
36 regmap = <&rcc>;
37 offset = <0x404>;
38 mask = <0x1>;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010039 };
40
41 soc {
42 u-boot,dm-pre-reloc;
Marek Vasuta8c97f42020-04-22 13:18:13 +020043
44 ddr: ddr@5a003000 {
45 u-boot,dm-pre-reloc;
46
47 compatible = "st,stm32mp1-ddr";
48
49 reg = <0x5A003000 0x550
50 0x5A004000 0x234>;
51
52 clocks = <&rcc AXIDCG>,
53 <&rcc DDRC1>,
54 <&rcc DDRC2>,
55 <&rcc DDRPHYC>,
56 <&rcc DDRCAPB>,
57 <&rcc DDRPHYCAPB>;
58
59 clock-names = "axidcg",
60 "ddrc1",
61 "ddrc2",
62 "ddrphyc",
63 "ddrcapb",
64 "ddrphycapb";
65
66 status = "okay";
67 };
Patrick Delaunaye16750f2018-03-20 11:45:14 +010068 };
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010069};
70
Patrick Delaunaybfe1f082019-02-27 17:01:27 +010071&bsec {
Patrick Delaunay95bd49a2020-05-25 12:19:41 +020072 u-boot,dm-pre-reloc;
Patrick Delaunay35a54d42019-07-11 11:15:28 +020073};
74
75&clk_csi {
Patrick Delaunaybfe1f082019-02-27 17:01:27 +010076 u-boot,dm-pre-reloc;
77};
78
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010079&clk_hsi {
80 u-boot,dm-pre-reloc;
81};
82
83&clk_hse {
84 u-boot,dm-pre-reloc;
85};
86
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010087&clk_lsi {
88 u-boot,dm-pre-reloc;
89};
90
Patrick Delaunay35a54d42019-07-11 11:15:28 +020091&clk_lse {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010092 u-boot,dm-pre-reloc;
93};
94
Patrick Delaunay4a87fea2020-05-25 12:19:48 +020095&cpu0_opp_table {
96 u-boot,dm-spl;
97 opp-650000000 {
98 u-boot,dm-spl;
99 };
100 opp-800000000 {
101 u-boot,dm-spl;
102 };
103};
104
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100105&gpioa {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100106 u-boot,dm-pre-reloc;
107};
108
109&gpiob {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100110 u-boot,dm-pre-reloc;
111};
112
113&gpioc {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100114 u-boot,dm-pre-reloc;
115};
116
117&gpiod {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100118 u-boot,dm-pre-reloc;
119};
120
121&gpioe {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100122 u-boot,dm-pre-reloc;
123};
124
125&gpiof {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100126 u-boot,dm-pre-reloc;
127};
128
129&gpiog {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100130 u-boot,dm-pre-reloc;
131};
132
133&gpioh {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100134 u-boot,dm-pre-reloc;
135};
136
137&gpioi {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100138 u-boot,dm-pre-reloc;
139};
140
141&gpioj {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100142 u-boot,dm-pre-reloc;
143};
144
145&gpiok {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100146 u-boot,dm-pre-reloc;
147};
148
149&gpioz {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100150 u-boot,dm-pre-reloc;
151};
Patrice Chotard75500a42019-04-30 17:26:21 +0200152
Patrick Delaunay6d923002019-07-30 19:16:14 +0200153&iwdg2 {
154 u-boot,dm-pre-reloc;
155};
156
Patrick Delaunay2c258092019-07-30 19:16:16 +0200157/* pre-reloc probe = reserve video frame buffer in video_reserve() */
158&ltdc {
159 u-boot,dm-pre-proper;
160};
161
Patrick Delaunay5a536df2020-10-15 15:01:12 +0200162/* temp = waiting kernel update */
163&m4_rproc {
164 resets = <&rcc MCU_R>,
165 <&rcc MCU_HOLD_BOOT_R>;
166 reset-names = "mcu_rst", "hold_boot";
167};
168
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200169&pinctrl {
Patrice Chotard75500a42019-04-30 17:26:21 +0200170 u-boot,dm-pre-reloc;
171};
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200172
173&pinctrl_z {
174 u-boot,dm-pre-reloc;
175};
176
Patrick Delaunay7915b992020-01-28 10:10:59 +0100177&pwr_regulators {
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200178 u-boot,dm-pre-reloc;
179};
180
181&rcc {
182 u-boot,dm-pre-reloc;
Patrick Delaunay8d93a972020-01-28 10:11:03 +0100183 #address-cells = <1>;
184 #size-cells = <0>;
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200185};
186
187&sdmmc1 {
188 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
189};
190
191&sdmmc2 {
192 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
193};
194
195&sdmmc3 {
196 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
197};
198
Patrick Delaunay0b733552020-07-06 14:48:58 +0200199&usart1 {
200 resets = <&rcc USART1_R>;
201};
202
203&usart2 {
204 resets = <&rcc USART2_R>;
205};
206
207&usart3 {
208 resets = <&rcc USART3_R>;
209};
210
211&uart4 {
212 resets = <&rcc UART4_R>;
213};
214
215&uart5 {
216 resets = <&rcc UART5_R>;
217};
218
219&usart6 {
220 resets = <&rcc USART6_R>;
221};
222
223&uart7 {
224 resets = <&rcc UART7_R>;
225};
226
227&uart8{
228 resets = <&rcc UART8_R>;
229};
230
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200231&usbotg_hs {
232 compatible = "st,stm32mp1-hsotg", "snps,dwc2";
233};