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Vitaly Andrianovef509b92014-04-04 13:16:53 -04001/*
Hao Zhange5951072014-07-09 23:44:46 +03002 * Keystone : Board initialization
Vitaly Andrianovef509b92014-04-04 13:16:53 -04003 *
Hao Zhange5951072014-07-09 23:44:46 +03004 * (C) Copyright 2014
Vitaly Andrianovef509b92014-04-04 13:16:53 -04005 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
Hao Zhange5951072014-07-09 23:44:46 +030010#include "board.h"
Vitaly Andrianovef509b92014-04-04 13:16:53 -040011#include <common.h>
12#include <exports.h>
13#include <fdt_support.h>
Khoronzhuk, Ivan0b868582014-07-09 19:48:40 +030014#include <asm/arch/ddr3.h>
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040015#include <asm/arch/emac_defs.h>
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030016#include <asm/ti-common/ti-aemif.h>
Vitaly Andrianovef509b92014-04-04 13:16:53 -040017
18DECLARE_GLOBAL_DATA_PTR;
19
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030020static struct aemif_config aemif_configs[] = {
Vitaly Andrianovef509b92014-04-04 13:16:53 -040021 { /* CS0 */
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030022 .mode = AEMIF_MODE_NAND,
Vitaly Andrianovef509b92014-04-04 13:16:53 -040023 .wr_setup = 0xf,
24 .wr_strobe = 0x3f,
25 .wr_hold = 7,
26 .rd_setup = 0xf,
27 .rd_strobe = 0x3f,
28 .rd_hold = 7,
29 .turn_around = 3,
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030030 .width = AEMIF_WIDTH_8,
Vitaly Andrianovef509b92014-04-04 13:16:53 -040031 },
Vitaly Andrianovef509b92014-04-04 13:16:53 -040032};
33
34int dram_init(void)
35{
Khoronzhuk, Ivan0b868582014-07-09 19:48:40 +030036 ddr3_init();
Vitaly Andrianovef509b92014-04-04 13:16:53 -040037
38 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
39 CONFIG_MAX_RAM_BANK_SIZE);
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030040 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040041 return 0;
42}
43
Hao Zhange5951072014-07-09 23:44:46 +030044int board_init(void)
45{
46 gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040047
Hao Zhange5951072014-07-09 23:44:46 +030048 return 0;
49}
50
51#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040052int get_eth_env_param(char *env_name)
53{
54 char *env;
Hao Zhange5951072014-07-09 23:44:46 +030055 int res = -1;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040056
57 env = getenv(env_name);
58 if (env)
59 res = simple_strtol(env, NULL, 0);
60
61 return res;
62}
63
64int board_eth_init(bd_t *bis)
65{
Hao Zhange5951072014-07-09 23:44:46 +030066 int j;
67 int res;
68 int port_num;
69 char link_type_name[32];
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040070
Hao Zhange5951072014-07-09 23:44:46 +030071 port_num = get_num_eth_ports();
72
73 for (j = 0; j < port_num; j++) {
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040074 sprintf(link_type_name, "sgmii%d_link_type", j);
75 res = get_eth_env_param(link_type_name);
76 if (res >= 0)
77 eth_priv_cfg[j].sgmii_link_type = res;
78
79 keystone2_emac_initialize(&eth_priv_cfg[j]);
80 }
81
82 return 0;
83}
84#endif
85
Vitaly Andrianovef509b92014-04-04 13:16:53 -040086#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Vitaly Andrianovef509b92014-04-04 13:16:53 -040087void ft_board_setup(void *blob, bd_t *bd)
88{
Hao Zhange5951072014-07-09 23:44:46 +030089 int lpae;
90 char *env;
91 char *endp;
Vitaly Andrianovef509b92014-04-04 13:16:53 -040092 int nbanks;
Hao Zhange5951072014-07-09 23:44:46 +030093 u64 size[2];
94 u64 start[2];
95 char name[32];
96 int nodeoffset;
97 u32 ddr3a_size;
98 int unitrd_fixup = 0;
Vitaly Andrianovef509b92014-04-04 13:16:53 -040099
100 env = getenv("mem_lpae");
101 lpae = env && simple_strtol(env, NULL, 0);
Murali Karicheri0bedbb82014-07-09 23:44:45 +0300102 env = getenv("uinitrd_fixup");
103 unitrd_fixup = env && simple_strtol(env, NULL, 0);
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400104
105 ddr3a_size = 0;
106 if (lpae) {
107 env = getenv("ddr3a_size");
108 if (env)
109 ddr3a_size = simple_strtol(env, NULL, 10);
110 if ((ddr3a_size != 8) && (ddr3a_size != 4))
111 ddr3a_size = 0;
112 }
113
114 nbanks = 1;
115 start[0] = bd->bi_dram[0].start;
116 size[0] = bd->bi_dram[0].size;
117
118 /* adjust memory start address for LPAE */
119 if (lpae) {
Hao Zhange5951072014-07-09 23:44:46 +0300120 start[0] -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400121 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
122 }
123
124 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
125 size[1] = ((u64)ddr3a_size - 2) << 30;
126 start[1] = 0x880000000;
127 nbanks++;
128 }
129
130 /* reserve memory at start of bank */
131 sprintf(name, "mem_reserve_head");
132 env = getenv(name);
133 if (env) {
134 start[0] += ustrtoul(env, &endp, 0);
135 size[0] -= ustrtoul(env, &endp, 0);
136 }
137
138 sprintf(name, "mem_reserve");
139 env = getenv(name);
140 if (env)
141 size[0] -= ustrtoul(env, &endp, 0);
142
143 fdt_fixup_memory_banks(blob, start, size, nbanks);
144
145 /* Fix up the initrd */
Murali Karicheri0bedbb82014-07-09 23:44:45 +0300146 if (lpae && unitrd_fixup) {
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400147 int err;
Hao Zhange5951072014-07-09 23:44:46 +0300148 u32 *prop1, *prop2;
149 u64 initrd_start, initrd_end;
Murali Karicheri0bedbb82014-07-09 23:44:45 +0300150
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400151 nodeoffset = fdt_path_offset(blob, "/chosen");
152 if (nodeoffset >= 0) {
153 prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
154 "linux,initrd-start", NULL);
155 prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
156 "linux,initrd-end", NULL);
157 if (prop1 && prop2) {
158 initrd_start = __be32_to_cpu(*prop1);
Hao Zhange5951072014-07-09 23:44:46 +0300159 initrd_start -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400160 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
161 initrd_start = __cpu_to_be64(initrd_start);
162 initrd_end = __be32_to_cpu(*prop2);
Hao Zhange5951072014-07-09 23:44:46 +0300163 initrd_end -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400164 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
165 initrd_end = __cpu_to_be64(initrd_end);
166
167 err = fdt_delprop(blob, nodeoffset,
168 "linux,initrd-start");
169 if (err < 0)
170 puts("error deleting initrd-start\n");
171
172 err = fdt_delprop(blob, nodeoffset,
173 "linux,initrd-end");
174 if (err < 0)
175 puts("error deleting initrd-end\n");
176
177 err = fdt_setprop(blob, nodeoffset,
178 "linux,initrd-start",
179 &initrd_start,
180 sizeof(initrd_start));
181 if (err < 0)
182 puts("error adding initrd-start\n");
183
184 err = fdt_setprop(blob, nodeoffset,
185 "linux,initrd-end",
186 &initrd_end,
187 sizeof(initrd_end));
188 if (err < 0)
189 puts("error adding linux,initrd-end\n");
190 }
191 }
192 }
193}
194
195void ft_board_setup_ex(void *blob, bd_t *bd)
196{
Hao Zhange5951072014-07-09 23:44:46 +0300197 int lpae;
198 u64 size;
199 char *env;
200 u64 *reserve_start;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400201
202 env = getenv("mem_lpae");
203 lpae = env && simple_strtol(env, NULL, 0);
204
205 if (lpae) {
206 /*
207 * the initrd and other reserved memory areas are
208 * embedded in in the DTB itslef. fix up these addresses
209 * to 36 bit format
210 */
211 reserve_start = (u64 *)((char *)blob +
212 fdt_off_mem_rsvmap(blob));
213 while (1) {
214 *reserve_start = __cpu_to_be64(*reserve_start);
215 size = __cpu_to_be64(*(reserve_start + 1));
216 if (size) {
Hao Zhange5951072014-07-09 23:44:46 +0300217 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400218 *reserve_start +=
219 CONFIG_SYS_LPAE_SDRAM_BASE;
220 *reserve_start =
221 __cpu_to_be64(*reserve_start);
222 } else {
223 break;
224 }
225 reserve_start += 2;
226 }
227 }
228}
229#endif