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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamadab21e20b2016-01-19 13:55:28 +09002/*
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadab21e20b2016-01-19 13:55:28 +09004 */
5
6#include <common.h>
Stephen Warren135aa952016-06-17 09:44:00 -06007#include <clk-uclass.h>
Simon Glass9d922452017-05-17 17:18:03 -06008#include <dm.h>
Peng Fan4f305bf2019-07-31 07:01:39 +00009#include <linux/clk-provider.h>
Masahiro Yamadab21e20b2016-01-19 13:55:28 +090010
Stephen Warren135aa952016-06-17 09:44:00 -060011static ulong clk_fixed_rate_get_rate(struct clk *clk)
Masahiro Yamadab21e20b2016-01-19 13:55:28 +090012{
Stephen Warren135aa952016-06-17 09:44:00 -060013 return to_clk_fixed_rate(clk->dev)->fixed_rate;
Masahiro Yamadab21e20b2016-01-19 13:55:28 +090014}
15
Chunfeng Yun6bf6d812020-01-09 11:35:08 +080016/* avoid clk_enable() return -ENOSYS */
17static int dummy_enable(struct clk *clk)
18{
19 return 0;
20}
21
Masahiro Yamadab21e20b2016-01-19 13:55:28 +090022const struct clk_ops clk_fixed_rate_ops = {
23 .get_rate = clk_fixed_rate_get_rate,
Chunfeng Yun6bf6d812020-01-09 11:35:08 +080024 .enable = dummy_enable,
Masahiro Yamadab21e20b2016-01-19 13:55:28 +090025};
26
Simon Glassd1998a92020-12-03 16:55:21 -070027static int clk_fixed_rate_of_to_plat(struct udevice *dev)
Masahiro Yamadab21e20b2016-01-19 13:55:28 +090028{
Lukasz Majewski36bac0a2019-06-24 15:50:40 +020029 struct clk *clk = &to_clk_fixed_rate(dev)->clk;
Simon Glass7423daa2016-07-04 11:58:03 -060030#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Mario Sixe2db9e72018-01-15 11:06:52 +010031 to_clk_fixed_rate(dev)->fixed_rate =
32 dev_read_u32_default(dev, "clock-frequency", 0);
Simon Glass7423daa2016-07-04 11:58:03 -060033#endif
Lukasz Majewski36bac0a2019-06-24 15:50:40 +020034 /* Make fixed rate clock accessible from higher level struct clk */
35 dev->uclass_priv = clk;
36 clk->dev = dev;
Peng Fane6849e22019-08-21 13:35:03 +000037 clk->enable_count = 0;
Masahiro Yamadab21e20b2016-01-19 13:55:28 +090038
39 return 0;
40}
41
42static const struct udevice_id clk_fixed_rate_match[] = {
43 {
44 .compatible = "fixed-clock",
45 },
46 { /* sentinel */ }
47};
48
Simon Glass88280522020-10-03 11:31:32 -060049U_BOOT_DRIVER(fixed_clock) = {
50 .name = "fixed_clock",
Masahiro Yamadab21e20b2016-01-19 13:55:28 +090051 .id = UCLASS_CLK,
52 .of_match = clk_fixed_rate_match,
Simon Glassd1998a92020-12-03 16:55:21 -070053 .of_to_plat = clk_fixed_rate_of_to_plat,
Simon Glasscaa4daa2020-12-03 16:55:18 -070054 .plat_auto = sizeof(struct clk_fixed_rate),
Masahiro Yamadab21e20b2016-01-19 13:55:28 +090055 .ops = &clk_fixed_rate_ops,
Michal Simek4ab38172020-09-16 13:20:55 +020056 .flags = DM_FLAG_PRE_RELOC,
Masahiro Yamadab21e20b2016-01-19 13:55:28 +090057};