Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 1 | /* |
Cyril Chemparathy | 678e008 | 2010-06-07 14:13:27 -0400 | [diff] [blame] | 2 | * armboot - Startup Code for ARM1176 CPU-core |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 3 | * |
| 4 | * Copyright (c) 2007 Samsung Electronics |
| 5 | * |
| 6 | * Copyright (C) 2008 |
| 7 | * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | * |
| 27 | * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) |
| 28 | * 2007-09-21 - Added MoviNAND and OneNAND boot codes by |
| 29 | * jsgood (jsgood.yang@samsung.com) |
| 30 | * Base codes by scsuh (sc.suh) |
| 31 | */ |
| 32 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 33 | #include <asm-offsets.h> |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 34 | #include <config.h> |
| 35 | #include <version.h> |
| 36 | #ifdef CONFIG_ENABLE_MMU |
| 37 | #include <asm/proc/domain.h> |
| 38 | #endif |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 39 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 40 | #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) |
| 41 | #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 42 | #endif |
| 43 | |
| 44 | /* |
| 45 | ************************************************************************* |
| 46 | * |
| 47 | * Jump vector table as in table 3.1 in [1] |
| 48 | * |
| 49 | ************************************************************************* |
| 50 | */ |
| 51 | |
| 52 | .globl _start |
| 53 | _start: b reset |
| 54 | #ifndef CONFIG_NAND_SPL |
| 55 | ldr pc, _undefined_instruction |
| 56 | ldr pc, _software_interrupt |
| 57 | ldr pc, _prefetch_abort |
| 58 | ldr pc, _data_abort |
| 59 | ldr pc, _not_used |
| 60 | ldr pc, _irq |
| 61 | ldr pc, _fiq |
| 62 | |
| 63 | _undefined_instruction: |
| 64 | .word undefined_instruction |
| 65 | _software_interrupt: |
| 66 | .word software_interrupt |
| 67 | _prefetch_abort: |
| 68 | .word prefetch_abort |
| 69 | _data_abort: |
| 70 | .word data_abort |
| 71 | _not_used: |
| 72 | .word not_used |
| 73 | _irq: |
| 74 | .word irq |
| 75 | _fiq: |
| 76 | .word fiq |
| 77 | _pad: |
| 78 | .word 0x12345678 /* now 16*4=64 */ |
| 79 | #else |
| 80 | . = _start + 64 |
| 81 | #endif |
| 82 | |
| 83 | .global _end_vect |
| 84 | _end_vect: |
| 85 | .balignl 16,0xdeadbeef |
| 86 | /* |
| 87 | ************************************************************************* |
| 88 | * |
| 89 | * Startup Code (reset vector) |
| 90 | * |
| 91 | * do important init only if we don't start from memory! |
| 92 | * setup Memory and board specific bits prior to relocation. |
| 93 | * relocate armboot to ram |
| 94 | * setup stack |
| 95 | * |
| 96 | ************************************************************************* |
| 97 | */ |
| 98 | |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 99 | .globl _TEXT_BASE |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 100 | _TEXT_BASE: |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 101 | .word CONFIG_SYS_TEXT_BASE |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 102 | |
| 103 | /* |
| 104 | * Below variable is very important because we use MMU in U-Boot. |
| 105 | * Without it, we cannot run code correctly before MMU is ON. |
| 106 | * by scsuh. |
| 107 | */ |
| 108 | _TEXT_PHY_BASE: |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | .word CONFIG_SYS_PHY_UBOOT_BASE |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 110 | |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 111 | #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 112 | .globl _armboot_start |
| 113 | _armboot_start: |
| 114 | .word _start |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 115 | #endif |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 116 | |
| 117 | /* |
| 118 | * These are defined in the board-specific linker script. |
| 119 | */ |
| 120 | .globl _bss_start |
| 121 | _bss_start: |
| 122 | .word __bss_start |
| 123 | |
| 124 | .globl _bss_end |
| 125 | _bss_end: |
| 126 | .word _end |
| 127 | |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 128 | #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) |
| 129 | /* IRQ stack memory (calculated at run-time) + 8 bytes */ |
| 130 | .globl IRQ_STACK_START_IN |
| 131 | IRQ_STACK_START_IN: |
| 132 | .word 0x0badc0de |
| 133 | |
| 134 | .globl _datarel_start |
| 135 | _datarel_start: |
| 136 | .word __datarel_start |
| 137 | |
| 138 | .globl _datarelrolocal_start |
| 139 | _datarelrolocal_start: |
| 140 | .word __datarelrolocal_start |
| 141 | |
| 142 | .globl _datarellocal_start |
| 143 | _datarellocal_start: |
| 144 | .word __datarellocal_start |
| 145 | |
| 146 | .globl _datarelro_start |
| 147 | _datarelro_start: |
| 148 | .word __datarelro_start |
| 149 | |
| 150 | .globl _got_start |
| 151 | _got_start: |
| 152 | .word __got_start |
| 153 | |
| 154 | .globl _got_end |
| 155 | _got_end: |
| 156 | .word __got_end |
| 157 | |
| 158 | /* |
| 159 | * the actual reset code |
| 160 | */ |
| 161 | |
| 162 | reset: |
| 163 | /* |
| 164 | * set the cpu to SVC32 mode |
| 165 | */ |
| 166 | mrs r0, cpsr |
| 167 | bic r0, r0, #0x3f |
| 168 | orr r0, r0, #0xd3 |
| 169 | msr cpsr, r0 |
| 170 | |
| 171 | /* |
| 172 | ************************************************************************* |
| 173 | * |
| 174 | * CPU_init_critical registers |
| 175 | * |
| 176 | * setup important registers |
| 177 | * setup memory timing |
| 178 | * |
| 179 | ************************************************************************* |
| 180 | */ |
| 181 | /* |
| 182 | * we do sys-critical inits only at reboot, |
| 183 | * not when booting from ram! |
| 184 | */ |
| 185 | cpu_init_crit: |
| 186 | /* |
| 187 | * When booting from NAND - it has definitely been a reset, so, no need |
| 188 | * to flush caches and disable the MMU |
| 189 | */ |
| 190 | #ifndef CONFIG_NAND_SPL |
| 191 | /* |
| 192 | * flush v4 I/D caches |
| 193 | */ |
| 194 | mov r0, #0 |
| 195 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
| 196 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
| 197 | |
| 198 | /* |
| 199 | * disable MMU stuff and caches |
| 200 | */ |
| 201 | mrc p15, 0, r0, c1, c0, 0 |
| 202 | bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) |
| 203 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) |
| 204 | orr r0, r0, #0x00000002 @ set bit 2 (A) Align |
| 205 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache |
| 206 | |
| 207 | /* Prepare to disable the MMU */ |
| 208 | adr r2, mmu_disable_phys |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 209 | sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 210 | b mmu_disable |
| 211 | |
| 212 | .align 5 |
| 213 | /* Run in a single cache-line */ |
| 214 | mmu_disable: |
| 215 | mcr p15, 0, r0, c1, c0, 0 |
| 216 | nop |
| 217 | nop |
| 218 | mov pc, r2 |
| 219 | mmu_disable_phys: |
| 220 | |
| 221 | #ifdef CONFIG_DISABLE_TCM |
| 222 | /* |
| 223 | * Disable the TCMs |
| 224 | */ |
| 225 | mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ |
| 226 | cmp r0, #0 |
| 227 | beq skip_tcmdisable |
| 228 | mov r1, #0 |
| 229 | mov r2, #1 |
| 230 | tst r0, r2 |
| 231 | mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ |
| 232 | tst r0, r2, LSL #16 |
| 233 | mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ |
| 234 | skip_tcmdisable: |
| 235 | #endif |
| 236 | #endif |
| 237 | |
| 238 | #ifdef CONFIG_PERIPORT_REMAP |
| 239 | /* Peri port setup */ |
| 240 | ldr r0, =CONFIG_PERIPORT_BASE |
| 241 | orr r0, r0, #CONFIG_PERIPORT_SIZE |
| 242 | mcr p15,0,r0,c15,c2,4 |
| 243 | #endif |
| 244 | |
| 245 | /* |
| 246 | * Go setup Memory and board specific bits prior to relocation. |
| 247 | */ |
| 248 | bl lowlevel_init /* go setup pll,mux,memory */ |
| 249 | |
| 250 | /* Set stackpointer in internal RAM to call board_init_f */ |
| 251 | call_board_init_f: |
| 252 | ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) |
| 253 | ldr r0,=0x00000000 |
| 254 | bl board_init_f |
| 255 | |
| 256 | /*------------------------------------------------------------------------------*/ |
| 257 | |
| 258 | /* |
| 259 | * void relocate_code (addr_sp, gd, addr_moni) |
| 260 | * |
| 261 | * This "function" does not return, instead it continues in RAM |
| 262 | * after relocating the monitor code. |
| 263 | * |
| 264 | */ |
| 265 | .globl relocate_code |
| 266 | relocate_code: |
| 267 | mov r4, r0 /* save addr_sp */ |
| 268 | mov r5, r1 /* save addr of gd */ |
| 269 | mov r6, r2 /* save addr of destination */ |
| 270 | mov r7, r2 /* save addr of destination */ |
| 271 | |
| 272 | /* Set up the stack */ |
| 273 | stack_setup: |
| 274 | mov sp, r4 |
| 275 | |
| 276 | adr r0, _start |
| 277 | ldr r2, _TEXT_BASE |
| 278 | ldr r3, _bss_start |
| 279 | sub r2, r3, r2 /* r2 <- size of armboot */ |
| 280 | add r2, r0, r2 /* r2 <- source end address */ |
| 281 | cmp r0, r6 |
| 282 | beq clear_bss |
| 283 | |
| 284 | #ifndef CONFIG_SKIP_RELOCATE_UBOOT |
| 285 | copy_loop: |
| 286 | ldmia r0!, {r9-r10} /* copy from source address [r0] */ |
| 287 | stmia r6!, {r9-r10} /* copy to target address [r1] */ |
Albert Aribaud | da90d4c | 2010-10-05 16:06:39 +0200 | [diff] [blame] | 288 | cmp r0, r2 /* until source end address [r2] */ |
| 289 | blo copy_loop |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 290 | |
| 291 | #ifndef CONFIG_PRELOADER |
| 292 | /* fix got entries */ |
| 293 | ldr r1, _TEXT_BASE /* Text base */ |
| 294 | mov r0, r7 /* reloc addr */ |
| 295 | ldr r2, _got_start /* addr in Flash */ |
| 296 | ldr r3, _got_end /* addr in Flash */ |
| 297 | sub r3, r3, r1 |
| 298 | add r3, r3, r0 |
| 299 | sub r2, r2, r1 |
| 300 | add r2, r2, r0 |
| 301 | |
| 302 | fixloop: |
| 303 | ldr r4, [r2] |
| 304 | sub r4, r4, r1 |
| 305 | add r4, r4, r0 |
| 306 | str r4, [r2] |
| 307 | add r2, r2, #4 |
| 308 | cmp r2, r3 |
| 309 | bne fixloop |
| 310 | #endif |
| 311 | #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ |
| 312 | |
| 313 | #ifdef CONFIG_ENABLE_MMU |
| 314 | enable_mmu: |
| 315 | /* enable domain access */ |
| 316 | ldr r5, =0x0000ffff |
| 317 | mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ |
| 318 | |
| 319 | /* Set the TTB register */ |
| 320 | ldr r0, _mmu_table_base |
| 321 | ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE |
| 322 | ldr r2, =0xfff00000 |
| 323 | bic r0, r0, r2 |
| 324 | orr r1, r0, r1 |
| 325 | mcr p15, 0, r1, c2, c0, 0 |
| 326 | |
| 327 | /* Enable the MMU */ |
| 328 | mrc p15, 0, r0, c1, c0, 0 |
| 329 | orr r0, r0, #1 /* Set CR_M to enable MMU */ |
| 330 | |
| 331 | /* Prepare to enable the MMU */ |
| 332 | adr r1, skip_hw_init |
| 333 | and r1, r1, #0x3fc |
| 334 | ldr r2, _TEXT_BASE |
| 335 | ldr r3, =0xfff00000 |
| 336 | and r2, r2, r3 |
| 337 | orr r2, r2, r1 |
| 338 | b mmu_enable |
| 339 | |
| 340 | .align 5 |
| 341 | /* Run in a single cache-line */ |
| 342 | mmu_enable: |
| 343 | |
| 344 | mcr p15, 0, r0, c1, c0, 0 |
| 345 | nop |
| 346 | nop |
| 347 | mov pc, r2 |
| 348 | skip_hw_init: |
| 349 | #endif |
| 350 | |
| 351 | clear_bss: |
| 352 | #ifndef CONFIG_PRELOADER |
| 353 | ldr r0, _bss_start |
| 354 | ldr r1, _bss_end |
| 355 | ldr r3, _TEXT_BASE /* Text base */ |
| 356 | mov r4, r7 /* reloc addr */ |
| 357 | sub r0, r0, r3 |
| 358 | add r0, r0, r4 |
| 359 | sub r1, r1, r3 |
| 360 | add r1, r1, r4 |
| 361 | mov r2, #0x00000000 /* clear */ |
| 362 | |
| 363 | clbss_l:str r2, [r0] /* clear loop... */ |
| 364 | add r0, r0, #4 |
| 365 | cmp r0, r1 |
| 366 | bne clbss_l |
| 367 | |
| 368 | bl coloured_LED_init |
| 369 | bl red_LED_on |
| 370 | #endif |
| 371 | |
| 372 | /* |
| 373 | * We are done. Do not return, instead branch to second part of board |
| 374 | * initialization, now running from RAM. |
| 375 | */ |
| 376 | #ifdef CONFIG_NAND_SPL |
| 377 | ldr pc, _nand_boot |
| 378 | |
| 379 | _nand_boot: .word nand_boot |
| 380 | #else |
| 381 | ldr r0, _TEXT_BASE |
| 382 | ldr r2, _board_init_r |
| 383 | sub r2, r2, r0 |
| 384 | add r2, r2, r7 /* position from board_init_r in RAM */ |
| 385 | /* setup parameters for board_init_r */ |
| 386 | mov r0, r5 /* gd_t */ |
| 387 | mov r1, r7 /* dest_addr */ |
| 388 | /* jump to it ... */ |
| 389 | mov lr, r2 |
| 390 | mov pc, lr |
| 391 | |
| 392 | _board_init_r: .word board_init_r |
| 393 | #endif |
| 394 | |
| 395 | #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ |
| 396 | |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 397 | /* |
| 398 | * the actual reset code |
| 399 | */ |
| 400 | |
| 401 | reset: |
| 402 | /* |
| 403 | * set the cpu to SVC32 mode |
| 404 | */ |
| 405 | mrs r0, cpsr |
| 406 | bic r0, r0, #0x3f |
| 407 | orr r0, r0, #0xd3 |
| 408 | msr cpsr, r0 |
| 409 | |
| 410 | /* |
| 411 | ************************************************************************* |
| 412 | * |
| 413 | * CPU_init_critical registers |
| 414 | * |
| 415 | * setup important registers |
| 416 | * setup memory timing |
| 417 | * |
| 418 | ************************************************************************* |
| 419 | */ |
| 420 | /* |
| 421 | * we do sys-critical inits only at reboot, |
| 422 | * not when booting from ram! |
| 423 | */ |
| 424 | cpu_init_crit: |
| 425 | /* |
| 426 | * When booting from NAND - it has definitely been a reset, so, no need |
| 427 | * to flush caches and disable the MMU |
| 428 | */ |
| 429 | #ifndef CONFIG_NAND_SPL |
| 430 | /* |
| 431 | * flush v4 I/D caches |
| 432 | */ |
| 433 | mov r0, #0 |
| 434 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
| 435 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
| 436 | |
| 437 | /* |
| 438 | * disable MMU stuff and caches |
| 439 | */ |
| 440 | mrc p15, 0, r0, c1, c0, 0 |
| 441 | bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) |
| 442 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) |
| 443 | orr r0, r0, #0x00000002 @ set bit 2 (A) Align |
| 444 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache |
Cyril Chemparathy | 678e008 | 2010-06-07 14:13:27 -0400 | [diff] [blame] | 445 | |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 446 | /* Prepare to disable the MMU */ |
Cyril Chemparathy | 678e008 | 2010-06-07 14:13:27 -0400 | [diff] [blame] | 447 | adr r2, mmu_disable_phys |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 448 | sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 449 | b mmu_disable |
| 450 | |
| 451 | .align 5 |
| 452 | /* Run in a single cache-line */ |
| 453 | mmu_disable: |
| 454 | mcr p15, 0, r0, c1, c0, 0 |
| 455 | nop |
| 456 | nop |
| 457 | mov pc, r2 |
Cyril Chemparathy | 678e008 | 2010-06-07 14:13:27 -0400 | [diff] [blame] | 458 | mmu_disable_phys: |
| 459 | |
| 460 | #ifdef CONFIG_DISABLE_TCM |
| 461 | /* |
| 462 | * Disable the TCMs |
| 463 | */ |
| 464 | mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ |
| 465 | cmp r0, #0 |
| 466 | beq skip_tcmdisable |
| 467 | mov r1, #0 |
| 468 | mov r2, #1 |
| 469 | tst r0, r2 |
| 470 | mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ |
| 471 | tst r0, r2, LSL #16 |
| 472 | mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ |
| 473 | skip_tcmdisable: |
| 474 | #endif |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 475 | #endif |
| 476 | |
Cyril Chemparathy | 678e008 | 2010-06-07 14:13:27 -0400 | [diff] [blame] | 477 | #ifdef CONFIG_PERIPORT_REMAP |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 478 | /* Peri port setup */ |
Cyril Chemparathy | 678e008 | 2010-06-07 14:13:27 -0400 | [diff] [blame] | 479 | ldr r0, =CONFIG_PERIPORT_BASE |
| 480 | orr r0, r0, #CONFIG_PERIPORT_SIZE |
| 481 | mcr p15,0,r0,c15,c2,4 |
Joonyoung Shim | 7b92159 | 2010-02-08 22:00:52 +0900 | [diff] [blame] | 482 | #endif |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 483 | |
| 484 | /* |
| 485 | * Go setup Memory and board specific bits prior to relocation. |
| 486 | */ |
| 487 | bl lowlevel_init /* go setup pll,mux,memory */ |
| 488 | |
Cyril Chemparathy | 678e008 | 2010-06-07 14:13:27 -0400 | [diff] [blame] | 489 | #ifndef CONFIG_SKIP_RELOCATE_UBOOT |
| 490 | relocate: /* relocate U-Boot to RAM */ |
| 491 | adr r0, _start /* r0 <- current position of code */ |
| 492 | ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ |
| 493 | cmp r0, r1 /* don't reloc during debug */ |
| 494 | beq stack_setup |
| 495 | |
| 496 | ldr r2, _armboot_start |
| 497 | ldr r3, _bss_start |
| 498 | sub r2, r3, r2 /* r2 <- size of armboot */ |
| 499 | add r2, r0, r2 /* r2 <- source end address */ |
| 500 | |
| 501 | copy_loop: |
| 502 | ldmia r0!, {r3-r10} /* copy from source address [r0] */ |
| 503 | stmia r1!, {r3-r10} /* copy to target address [r1] */ |
Albert Aribaud | da90d4c | 2010-10-05 16:06:39 +0200 | [diff] [blame] | 504 | cmp r0, r2 /* until source end address [r2] */ |
| 505 | blo copy_loop |
Cyril Chemparathy | 678e008 | 2010-06-07 14:13:27 -0400 | [diff] [blame] | 506 | #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ |
| 507 | |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 508 | #ifdef CONFIG_ENABLE_MMU |
| 509 | enable_mmu: |
| 510 | /* enable domain access */ |
| 511 | ldr r5, =0x0000ffff |
| 512 | mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ |
| 513 | |
| 514 | /* Set the TTB register */ |
| 515 | ldr r0, _mmu_table_base |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 516 | ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 517 | ldr r2, =0xfff00000 |
| 518 | bic r0, r0, r2 |
| 519 | orr r1, r0, r1 |
| 520 | mcr p15, 0, r1, c2, c0, 0 |
| 521 | |
| 522 | /* Enable the MMU */ |
| 523 | mrc p15, 0, r0, c1, c0, 0 |
| 524 | orr r0, r0, #1 /* Set CR_M to enable MMU */ |
| 525 | |
| 526 | /* Prepare to enable the MMU */ |
| 527 | adr r1, skip_hw_init |
| 528 | and r1, r1, #0x3fc |
| 529 | ldr r2, _TEXT_BASE |
| 530 | ldr r3, =0xfff00000 |
| 531 | and r2, r2, r3 |
| 532 | orr r2, r2, r1 |
| 533 | b mmu_enable |
| 534 | |
| 535 | .align 5 |
| 536 | /* Run in a single cache-line */ |
| 537 | mmu_enable: |
| 538 | |
| 539 | mcr p15, 0, r0, c1, c0, 0 |
| 540 | nop |
| 541 | nop |
| 542 | mov pc, r2 |
Cyril Chemparathy | 678e008 | 2010-06-07 14:13:27 -0400 | [diff] [blame] | 543 | skip_hw_init: |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 544 | #endif |
| 545 | |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 546 | /* Set up the stack */ |
| 547 | stack_setup: |
Seunghyeon Rhee | a59a23d | 2009-11-13 16:49:41 +0900 | [diff] [blame] | 548 | ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 549 | sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 550 | sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */ |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 551 | sub sp, r0, #12 /* leave 3 words for abort-stack */ |
Vitaly Kuzmichev | 1a27f7d | 2010-06-15 22:18:11 +0400 | [diff] [blame] | 552 | bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 553 | |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 554 | clear_bss: |
| 555 | ldr r0, _bss_start /* find start of bss segment */ |
| 556 | ldr r1, _bss_end /* stop here */ |
| 557 | mov r2, #0 /* clear */ |
| 558 | |
| 559 | clbss_l: |
| 560 | str r2, [r0] /* clear loop... */ |
| 561 | add r0, r0, #4 |
| 562 | cmp r0, r1 |
Albert Aribaud | da90d4c | 2010-10-05 16:06:39 +0200 | [diff] [blame] | 563 | blo clbss_l |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 564 | |
| 565 | #ifndef CONFIG_NAND_SPL |
| 566 | ldr pc, _start_armboot |
| 567 | |
| 568 | _start_armboot: |
| 569 | .word start_armboot |
| 570 | #else |
| 571 | b nand_boot |
| 572 | /* .word nand_boot*/ |
| 573 | #endif |
| 574 | |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 575 | #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ |
| 576 | |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 577 | #ifdef CONFIG_ENABLE_MMU |
| 578 | _mmu_table_base: |
| 579 | .word mmu_table |
| 580 | #endif |
| 581 | |
| 582 | #ifndef CONFIG_NAND_SPL |
| 583 | /* |
| 584 | * we assume that cache operation is done before. (eg. cleanup_before_linux()) |
| 585 | * actually, we don't need to do anything about cache if not use d-cache in |
| 586 | * U-Boot. So, in this function we clean only MMU. by scsuh |
| 587 | * |
| 588 | * void theLastJump(void *kernel, int arch_num, uint boot_params); |
| 589 | */ |
| 590 | #ifdef CONFIG_ENABLE_MMU |
| 591 | .globl theLastJump |
| 592 | theLastJump: |
| 593 | mov r9, r0 |
| 594 | ldr r3, =0xfff00000 |
| 595 | ldr r4, _TEXT_PHY_BASE |
| 596 | adr r5, phy_last_jump |
| 597 | bic r5, r5, r3 |
| 598 | orr r5, r5, r4 |
| 599 | mov pc, r5 |
| 600 | phy_last_jump: |
| 601 | /* |
| 602 | * disable MMU stuff |
| 603 | */ |
| 604 | mrc p15, 0, r0, c1, c0, 0 |
| 605 | bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ |
| 606 | bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ |
| 607 | orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ |
| 608 | orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ |
| 609 | mcr p15, 0, r0, c1, c0, 0 |
| 610 | |
| 611 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
| 612 | |
| 613 | mov r0, #0 |
| 614 | mov pc, r9 |
| 615 | #endif |
Cyril Chemparathy | 678e008 | 2010-06-07 14:13:27 -0400 | [diff] [blame] | 616 | |
| 617 | |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 618 | /* |
| 619 | ************************************************************************* |
| 620 | * |
| 621 | * Interrupt handling |
| 622 | * |
| 623 | ************************************************************************* |
| 624 | */ |
| 625 | @ |
| 626 | @ IRQ stack frame. |
| 627 | @ |
| 628 | #define S_FRAME_SIZE 72 |
| 629 | |
| 630 | #define S_OLD_R0 68 |
| 631 | #define S_PSR 64 |
| 632 | #define S_PC 60 |
| 633 | #define S_LR 56 |
| 634 | #define S_SP 52 |
| 635 | |
| 636 | #define S_IP 48 |
| 637 | #define S_FP 44 |
| 638 | #define S_R10 40 |
| 639 | #define S_R9 36 |
| 640 | #define S_R8 32 |
| 641 | #define S_R7 28 |
| 642 | #define S_R6 24 |
| 643 | #define S_R5 20 |
| 644 | #define S_R4 16 |
| 645 | #define S_R3 12 |
| 646 | #define S_R2 8 |
| 647 | #define S_R1 4 |
| 648 | #define S_R0 0 |
| 649 | |
| 650 | #define MODE_SVC 0x13 |
| 651 | #define I_BIT 0x80 |
| 652 | |
| 653 | /* |
| 654 | * use bad_save_user_regs for abort/prefetch/undef/swi ... |
| 655 | */ |
| 656 | |
| 657 | .macro bad_save_user_regs |
| 658 | /* carve out a frame on current user stack */ |
| 659 | sub sp, sp, #S_FRAME_SIZE |
| 660 | /* Save user registers (now in svc mode) r0-r12 */ |
| 661 | stmia sp, {r0 - r12} |
| 662 | |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 663 | #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 664 | ldr r2, _armboot_start |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 665 | sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 666 | /* set base 2 words into abort stack */ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 667 | sub r2, r2, #(GENERATED_GBL_DATA_SIZE+8) |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 668 | #else |
| 669 | ldr r2, IRQ_STACK_START_IN |
| 670 | #endif |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 671 | /* get values for "aborted" pc and cpsr (into parm regs) */ |
| 672 | ldmia r2, {r2 - r3} |
| 673 | /* grab pointer to old stack */ |
| 674 | add r0, sp, #S_FRAME_SIZE |
| 675 | |
| 676 | add r5, sp, #S_SP |
| 677 | mov r1, lr |
| 678 | /* save sp_SVC, lr_SVC, pc, cpsr */ |
| 679 | stmia r5, {r0 - r3} |
| 680 | /* save current stack into r0 (param register) */ |
| 681 | mov r0, sp |
| 682 | .endm |
| 683 | |
| 684 | .macro get_bad_stack |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 685 | #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 686 | /* setup our mode stack (enter in banked mode) */ |
| 687 | ldr r13, _armboot_start |
| 688 | /* move past malloc pool */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 689 | sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 690 | /* move to reserved a couple spots for abort stack */ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 691 | sub r13, r13, #(GENERATED_GBL_DATA_SIZE + 8) |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 692 | #else |
| 693 | ldr r13, IRQ_STACK_START_IN @ setup our mode stack |
| 694 | #endif |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 695 | |
| 696 | /* save caller lr in position 0 of saved stack */ |
| 697 | str lr, [r13] |
| 698 | /* get the spsr */ |
| 699 | mrs lr, spsr |
| 700 | /* save spsr in position 1 of saved stack */ |
| 701 | str lr, [r13, #4] |
| 702 | |
| 703 | /* prepare SVC-Mode */ |
| 704 | mov r13, #MODE_SVC |
| 705 | @ msr spsr_c, r13 |
| 706 | /* switch modes, make sure moves will execute */ |
| 707 | msr spsr, r13 |
| 708 | /* capture return pc */ |
| 709 | mov lr, pc |
| 710 | /* jump to next instruction & switch modes. */ |
| 711 | movs pc, lr |
| 712 | .endm |
| 713 | |
| 714 | .macro get_bad_stack_swi |
| 715 | /* space on current stack for scratch reg. */ |
| 716 | sub r13, r13, #4 |
| 717 | /* save R0's value. */ |
| 718 | str r0, [r13] |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 719 | #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 720 | /* get data regions start */ |
| 721 | ldr r0, _armboot_start |
| 722 | /* move past malloc pool */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 723 | sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 724 | /* move past gbl and a couple spots for abort stack */ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 725 | sub r0, r0, #(GENERATED_GBL_DATA_SIZE + 8) |
Heiko Schocher | a51dd67 | 2010-09-17 13:10:53 +0200 | [diff] [blame] | 726 | #else |
| 727 | ldr r13, IRQ_STACK_START_IN @ setup our mode stack |
| 728 | #endif |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 729 | /* save caller lr in position 0 of saved stack */ |
| 730 | str lr, [r0] |
| 731 | /* get the spsr */ |
| 732 | mrs r0, spsr |
| 733 | /* save spsr in position 1 of saved stack */ |
| 734 | str lr, [r0, #4] |
| 735 | /* restore r0 */ |
| 736 | ldr r0, [r13] |
| 737 | /* pop stack entry */ |
| 738 | add r13, r13, #4 |
| 739 | .endm |
| 740 | |
| 741 | /* |
| 742 | * exception handlers |
| 743 | */ |
| 744 | .align 5 |
| 745 | undefined_instruction: |
| 746 | get_bad_stack |
| 747 | bad_save_user_regs |
| 748 | bl do_undefined_instruction |
| 749 | |
| 750 | .align 5 |
| 751 | software_interrupt: |
| 752 | get_bad_stack_swi |
| 753 | bad_save_user_regs |
| 754 | bl do_software_interrupt |
| 755 | |
| 756 | .align 5 |
| 757 | prefetch_abort: |
| 758 | get_bad_stack |
| 759 | bad_save_user_regs |
| 760 | bl do_prefetch_abort |
| 761 | |
| 762 | .align 5 |
| 763 | data_abort: |
| 764 | get_bad_stack |
| 765 | bad_save_user_regs |
| 766 | bl do_data_abort |
| 767 | |
| 768 | .align 5 |
| 769 | not_used: |
| 770 | get_bad_stack |
| 771 | bad_save_user_regs |
| 772 | bl do_not_used |
| 773 | |
| 774 | .align 5 |
| 775 | irq: |
| 776 | get_bad_stack |
| 777 | bad_save_user_regs |
| 778 | bl do_irq |
| 779 | |
| 780 | .align 5 |
| 781 | fiq: |
| 782 | get_bad_stack |
| 783 | bad_save_user_regs |
| 784 | bl do_fiq |
| 785 | #endif /* CONFIG_NAND_SPL */ |