Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / 120e92d9693b445c8397c159d26f60e4dbeadc4d / . / configs / MPC8308RDB_defconfig
blob: 74eccf5b6ba9af27800622811a60844f4fbb8b09 [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]1CONFIG_PPC=y
Tom Rini278b90c2018-02-03 12:10:38 -0500[diff] [blame]2CONFIG_SYS_TEXT_BASE=0xFE000000
Tom Rinia09fea12019-11-18 20:02:10 -0500[diff] [blame]3CONFIG_ENV_SIZE=0x2000
4CONFIG_ENV_SECT_SIZE=0x10000
Mario Sixff3bb0c2019-01-21 09:17:53 +0100[diff] [blame]5CONFIG_SYS_CLK_FREQ=33333333
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]6CONFIG_MPC83xx=y
7CONFIG_TARGET_MPC8308RDB=y
Mario Six21c15022019-01-21 09:17:54 +0100[diff] [blame]8CONFIG_SYSTEM_PLL_VCO_DIV_2=y
9CONFIG_SYSTEM_PLL_FACTOR_4_1=y
10CONFIG_CORE_PLL_RATIO_3_1=y
11CONFIG_BOOT_MEMORY_SPACE_LOW=y
12CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
13CONFIG_TSEC1_MODE_RGMII=y
14CONFIG_TSEC2_MODE_RGMII=y
Mario Six30915ab2019-01-21 09:17:57 +0100[diff] [blame]15CONFIG_BAT0=y
16CONFIG_BAT0_NAME="DDR"
17CONFIG_BAT0_BASE=0x00000000
18CONFIG_BAT0_LENGTH_128_MBYTES=y
19CONFIG_BAT0_ACCESS_RW=y
20CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
21CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
22CONFIG_BAT0_USER_MODE_VALID=y
23CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
24CONFIG_BAT1=y
25CONFIG_BAT1_NAME="IMMRBAR"
26CONFIG_BAT1_BASE=0xE0000000
27CONFIG_BAT1_LENGTH_8_MBYTES=y
28CONFIG_BAT1_ACCESS_RW=y
29CONFIG_BAT1_ICACHE_INHIBITED=y
30CONFIG_BAT1_ICACHE_GUARDED=y
31CONFIG_BAT1_DCACHE_INHIBITED=y
32CONFIG_BAT1_DCACHE_GUARDED=y
33CONFIG_BAT1_USER_MODE_VALID=y
34CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
35CONFIG_BAT2=y
36CONFIG_BAT2_NAME="FLASH"
37CONFIG_BAT2_BASE=0xFE000000
38CONFIG_BAT2_LENGTH_8_MBYTES=y
39CONFIG_BAT2_ACCESS_RW=y
40CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
41CONFIG_BAT2_DCACHE_INHIBITED=y
42CONFIG_BAT2_DCACHE_GUARDED=y
43CONFIG_BAT2_USER_MODE_VALID=y
44CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
45CONFIG_BAT3=y
46CONFIG_BAT3_NAME="STACK_IN_DCACHE"
47CONFIG_BAT3_BASE=0xE6000000
48CONFIG_BAT3_ACCESS_RW=y
49CONFIG_BAT3_USER_MODE_VALID=y
50CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
Mario Six9c5df7a2019-01-21 09:17:58 +0100[diff] [blame]51CONFIG_LBLAW0=y
52CONFIG_LBLAW0_BASE=0xFE000000
53CONFIG_LBLAW0_NAME="FLASH"
54CONFIG_LBLAW0_LENGTH_8_MBYTES=y
55CONFIG_LBLAW1=y
56CONFIG_LBLAW1_BASE=0xE0600000
57CONFIG_LBLAW1_NAME="NAND"
58CONFIG_LBLAW1_LENGTH_32_KBYTES=y
59CONFIG_LBLAW2=y
60CONFIG_LBLAW2_BASE=0xF0000000
61CONFIG_LBLAW2_NAME="VSC7385"
62CONFIG_LBLAW2_LENGTH_128_KBYTES=y
Tom Rini344a0e42019-05-26 14:45:25 -0400[diff] [blame]63CONFIG_ELBC_BR0_OR0=y
64CONFIG_BR0_OR0_NAME="FLASH"
65CONFIG_BR0_OR0_BASE=0xFE000000
66CONFIG_BR0_PORTSIZE_16BIT=y
67CONFIG_OR0_AM_8_MBYTES=y
68CONFIG_OR0_XAM_SET=y
69CONFIG_OR0_SCY_15=y
70CONFIG_OR0_CSNT_EARLIER=y
71CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
72CONFIG_OR0_XACS_EXTENDED=y
73CONFIG_OR0_TRLX_RELAXED=y
74CONFIG_OR0_EHTR_8_CYCLE=y
75CONFIG_ELBC_BR1_OR1=y
76CONFIG_BR1_OR1_NAME="NAND"
77CONFIG_BR1_OR1_BASE=0xE0600000
78CONFIG_BR1_ERRORCHECKING_BOTH=y
79CONFIG_BR1_MACHINE_FCM=y
80CONFIG_OR1_SCY_1=y
81CONFIG_OR1_CSCT_8_CYCLE=y
82CONFIG_OR1_CST_ONE_CLOCK=y
83CONFIG_OR1_CHT_TWO_CLOCK=y
84CONFIG_OR1_TRLX_RELAXED=y
85CONFIG_OR1_EHTR_8_CYCLE=y
86CONFIG_ELBC_BR2_OR2=y
87CONFIG_BR2_OR2_NAME="VSC7385_BASE"
88CONFIG_BR2_OR2_BASE=0xF0000000
89CONFIG_OR2_AM_128_KBYTES=y
90CONFIG_OR2_SCY_15=y
91CONFIG_OR2_CSNT_EARLIER=y
92CONFIG_OR2_XACS_EXTENDED=y
93CONFIG_OR2_SETA_EXTERNAL=y
94CONFIG_OR2_TRLX_RELAXED=y
95CONFIG_OR2_EHTR_8_CYCLE=y
Mario Sixbe5abb02019-01-21 09:18:09 +0100[diff] [blame]96CONFIG_HID0_FINAL_EMCP=y
97CONFIG_HID0_FINAL_DPM=y
98CONFIG_HID0_FINAL_ICE=y
99CONFIG_HID2_HBE=y
Mario Sixba463c12019-01-21 09:18:11 +0100[diff] [blame]100CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
101CONFIG_SICR_GPIO_A_TSEC2=y
102CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y
103CONFIG_SICR_IEEE1588_A_GPIO=y
104CONFIG_SICR_GTM_GPIO=y
105CONFIG_SICR_GPIOSEL_IEEE1588=y
106CONFIG_SICR_TMSOBI1_2_5_V=y
107CONFIG_SICR_TMSOBI2_2_5_V=y
Mario Six73df96a2019-01-21 09:18:12 +0100[diff] [blame]108CONFIG_ACR_PIPE_DEP_4=y
109CONFIG_ACR_RPTCNT_4=y
Mario Sixe35012e2019-01-21 09:18:13 +0100[diff] [blame]110CONFIG_SPCR_TSECEP_3=y
Mario Six7c2e5352019-01-21 09:18:14 +0100[diff] [blame]111CONFIG_LCRR_DBYP_PLL_BYPASSED=y
112CONFIG_LCRR_CLKDIV_2=y
Simon Glass73223f02016-02-22 22:55:43 -0700[diff] [blame]113CONFIG_FIT=y
114CONFIG_FIT_VERBOSE=y
115CONFIG_OF_BOARD_SETUP=y
116CONFIG_OF_STDOUT_VIA_ALIAS=y
Heiko Schocherbb597c02016-06-07 08:31:14 +0200[diff] [blame]117CONFIG_BOOTDELAY=5
Adam Ford8ccf98b2018-07-29 13:13:29 -0500[diff] [blame]118CONFIG_MISC_INIT_R=y
Tom Riniadad96e2016-04-21 21:37:19 -0400[diff] [blame]119CONFIG_HUSH_PARSER=y
Adam Fordd021e942018-02-06 07:58:59 -0600[diff] [blame]120# CONFIG_AUTO_COMPLETE is not set
Tuomas Tynkkynenad12dc12017-10-08 21:48:01 +0300[diff] [blame]121CONFIG_CMD_IMLS=y
Tom Rini78d1e1d2016-04-22 16:41:25 -0400[diff] [blame]122CONFIG_CMD_I2C=y
Tom Rini88663122017-08-14 19:58:53 -0400[diff] [blame]123CONFIG_CMD_MMC=y
Simon Glass6500ec72017-08-04 16:34:34 -0600[diff] [blame]124CONFIG_CMD_PCI=y
Joe Hershbergeref0f2f52015-06-22 16:15:30 -0500[diff] [blame]125# CONFIG_CMD_SETEXPR is not set
Tom Rini78d1e1d2016-04-22 16:41:25 -0400[diff] [blame]126CONFIG_CMD_DHCP=y
Tom Rini89cb2b52016-04-24 17:29:26 -0400[diff] [blame]127CONFIG_CMD_MII=y
Tom Rini78d1e1d2016-04-22 16:41:25 -0400[diff] [blame]128CONFIG_CMD_PING=y
Chris Packhamc9032ce2017-04-29 15:20:28 +1200[diff] [blame]129CONFIG_CMD_DATE=y
Tom Rini89cb2b52016-04-24 17:29:26 -0400[diff] [blame]130CONFIG_CMD_FAT=y
Adam Forde91907a2020-07-03 06:48:56 -0500[diff] [blame]131CONFIG_ENV_OVERWRITE=y
Tom Rinicb6617a2019-11-10 11:28:03 -0500[diff] [blame]132CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
Tom Rinia09fea12019-11-18 20:02:10 -0500[diff] [blame]133CONFIG_ENV_ADDR=0xFE080000
134CONFIG_ENV_ADDR_REDUND=0xFE090000
Mario Six07dea2e2018-03-28 14:38:19 +0200[diff] [blame]135CONFIG_FSL_ESDHC=y
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900[diff] [blame]136CONFIG_MTD_NOR_FLASH=y
Adam Ford2fe88d42018-10-14 15:10:50 -0500[diff] [blame]137CONFIG_FLASH_CFI_DRIVER=y
138CONFIG_SYS_FLASH_PROTECTION=y
139CONFIG_SYS_FLASH_CFI=y
Tom Rini306881a2020-04-24 15:35:53 -0400[diff] [blame]140CONFIG_PHY_ATHEROS=y
141CONFIG_PHY_BROADCOM=y
142CONFIG_PHY_DAVICOM=y
143CONFIG_PHY_LXT=y
Mario Sixa8ca5c82018-04-27 14:52:21 +0200[diff] [blame]144CONFIG_PHY_MARVELL=y
Tom Rini306881a2020-04-24 15:35:53 -0400[diff] [blame]145CONFIG_PHY_NATSEMI=y
146CONFIG_PHY_REALTEK=y
147CONFIG_PHY_SMSC=y
148CONFIG_PHY_VITESSE=y
Adam Fordd7869b212018-07-20 23:03:57 -0500[diff] [blame]149CONFIG_MII=y
Mario Six17151052018-03-28 14:38:18 +0200[diff] [blame]150CONFIG_TSEC_ENET=y
Thomas Chou9e390032015-11-19 21:48:14 +0800[diff] [blame]151CONFIG_SYS_NS16550=y
Simon Glass69e173e2016-02-22 22:55:42 -0700[diff] [blame]152CONFIG_OF_LIBFDT=y