blob: 785d6129daf76e24ae3bf48c27757551b70f1092 [file] [log] [blame]
Scott Wood49ea3b62007-04-16 14:34:21 -05001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2007
3 *
4 * Author: Scott Wood <scottwood@freescale.com>,
5 * with some bits from older board-specific PCI initialization.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <pci.h>
Kim Phillips5c5d3242007-04-25 12:34:38 -050028#include <ft_build.h>
Scott Wood49ea3b62007-04-16 14:34:21 -050029#include <asm/mpc8349_pci.h>
30
31#ifdef CONFIG_83XX_GENERIC_PCI
32#define MAX_BUSES 2
33
34DECLARE_GLOBAL_DATA_PTR;
35
36static struct pci_controller pci_hose[MAX_BUSES];
37static int pci_num_buses;
38
39static void pci_init_bus(int bus, struct pci_region *reg)
40{
41 volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
42 volatile pot83xx_t *pot = immr->ios.pot;
43 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
44 struct pci_controller *hose = &pci_hose[bus];
45 u32 dev;
46 u16 reg16;
47 int i;
48
49 if (bus == 1)
50 pot += 3;
51
52 /* Setup outbound translation windows */
53 for (i = 0; i < 3; i++, reg++, pot++) {
54 if (reg->size == 0)
55 break;
56
57 hose->regions[i] = *reg;
58 hose->region_count++;
59
60 pot->potar = reg->bus_start >> 12;
61 pot->pobar = reg->phys_start >> 12;
62 pot->pocmr = ~(reg->size - 1) >> 12;
63
64 if (reg->flags & PCI_REGION_IO)
65 pot->pocmr |= POCMR_IO;
66#ifdef CONFIG_83XX_PCI_STREAMING
67 else if (reg->flags & PCI_REGION_PREFETCH)
68 pot->pocmr |= POCMR_SE;
69#endif
70
71 if (bus == 1)
72 pot->pocmr |= POCMR_DST;
73
74 pot->pocmr |= POCMR_EN;
75 }
76
77 /* Point inbound translation at RAM */
78 pci_ctrl->pitar1 = 0;
79 pci_ctrl->pibar1 = 0;
80 pci_ctrl->piebar1 = 0;
81 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
82 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
83
84 i = hose->region_count++;
85 hose->regions[i].bus_start = 0;
86 hose->regions[i].phys_start = 0;
87 hose->regions[i].size = gd->ram_size;
88 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
89
90 hose->first_busno = 0;
91 hose->last_busno = 0xff;
92
93 pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80,
94 CFG_IMMR + 0x8304 + bus * 0x80);
95
96 pci_register_hose(hose);
97
98 /*
99 * Write to Command register
100 */
101 reg16 = 0xff;
102 dev = PCI_BDF(hose->first_busno, 0, 0);
103 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
104 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
105 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
106
107 /*
108 * Clear non-reserved bits in status register.
109 */
110 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
111 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
112 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
113
114#ifdef CONFIG_PCI_SCAN_SHOW
115 printf("PCI: Bus Dev VenId DevId Class Int\n");
116#endif
117 /*
118 * Hose scan.
119 */
120 hose->last_busno = pci_hose_scan(hose);
121}
122
123/*
124 * The caller must have already set OCCR, and the PCI_LAW BARs
125 * must have been set to cover all of the requested regions.
126 *
127 * If fewer than three regions are requested, then the region
128 * list is terminated with a region of size 0.
129 */
130void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
131{
132 volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
133 int i;
134
135 if (num_buses > MAX_BUSES) {
136 printf("%d PCI buses requsted, %d supported\n",
137 num_buses, MAX_BUSES);
138
139 num_buses = MAX_BUSES;
140 }
141
142 pci_num_buses = num_buses;
143
144 /*
145 * Release PCI RST Output signal.
146 * Power on to RST high must be at least 100 ms as per PCI spec.
147 * On warm boots only 1 ms is required.
148 */
149 udelay(warmboot ? 1000 : 100000);
150
151 for (i = 0; i < num_buses; i++)
152 immr->pci_ctrl[i].gcr = 1;
153
154 /*
155 * RST high to first config access must be at least 2^25 cycles
156 * as per PCI spec. This could be cut in half if we know we're
157 * running at 66MHz. This could be insufficiently long if we're
158 * running the PCI bus at significantly less than 33MHz.
159 */
160 udelay(1020000);
161
162 for (i = 0; i < num_buses; i++)
163 pci_init_bus(i, reg[i]);
164}
165
166#ifdef CONFIG_OF_FLAT_TREE
167void ft_pci_setup(void *blob, bd_t *bd)
168{
169 u32 *p;
170 int len;
171
172 if (pci_num_buses < 1)
173 return;
174
175 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
176 if (p) {
177 p[0] = pci_hose[0].first_busno;
178 p[1] = pci_hose[0].last_busno;
179 }
180
181 if (pci_num_buses < 2)
182 return;
183
184 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
185 if (p) {
186 p[0] = pci_hose[1].first_busno;
187 p[1] = pci_hose[1].last_busno;
188 }
189}
190#endif /* CONFIG_OF_FLAT_TREE */
191
192#endif /* CONFIG_83XX_GENERIC_PCI */