blob: 17cbb0983db37f0e976b7fbd12bc208a70eabfbc [file] [log] [blame]
Sukumar Ghoraide941242010-09-18 20:32:33 -07001/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <common.h>
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020027#include <malloc.h>
Sukumar Ghoraide941242010-09-18 20:32:33 -070028#include <mmc.h>
29#include <part.h>
30#include <i2c.h>
31#include <twl4030.h>
Balaji T K14fa2dd2011-09-08 06:34:57 +000032#include <twl6030.h>
Nishanth Menoncb199102013-03-26 05:20:54 +000033#include <palmas.h>
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000034#include <asm/gpio.h>
Sukumar Ghoraide941242010-09-18 20:32:33 -070035#include <asm/io.h>
36#include <asm/arch/mmc_host_def.h>
Dirk Behme96e0e7b2011-05-15 09:04:47 +000037#include <asm/arch/sys_proto.h>
Sukumar Ghoraide941242010-09-18 20:32:33 -070038
Pantelis Antoniouab769f22014-02-26 19:28:45 +020039/* simplify defines to OMAP_HSMMC_USE_GPIO */
40#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
41 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
42#define OMAP_HSMMC_USE_GPIO
43#else
44#undef OMAP_HSMMC_USE_GPIO
45#endif
46
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +000047/* common definitions for all OMAPs */
48#define SYSCTL_SRC (1 << 25)
49#define SYSCTL_SRD (1 << 26)
50
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +000051struct omap_hsmmc_data {
52 struct hsmmc *base_addr;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020053 struct mmc_config cfg;
Pantelis Antoniouab769f22014-02-26 19:28:45 +020054#ifdef OMAP_HSMMC_USE_GPIO
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000055 int cd_gpio;
Nikita Kiryanove3913f52012-12-03 02:19:47 +000056 int wp_gpio;
Pantelis Antoniouab769f22014-02-26 19:28:45 +020057#endif
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +000058};
59
Nishanth Menoneb9a28f2010-11-19 11:18:12 -050060/* If we fail after 1 second wait, something is really bad */
61#define MAX_RETRY_MS 1000
62
Sricharan933efe62011-11-15 09:49:53 -050063static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
64static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
65 unsigned int siz);
Balaji T K14fa2dd2011-09-08 06:34:57 +000066
Pantelis Antoniouab769f22014-02-26 19:28:45 +020067#ifdef OMAP_HSMMC_USE_GPIO
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000068static int omap_mmc_setup_gpio_in(int gpio, const char *label)
69{
70 if (!gpio_is_valid(gpio))
71 return -1;
72
73 if (gpio_request(gpio, label) < 0)
74 return -1;
75
76 if (gpio_direction_input(gpio) < 0)
77 return -1;
78
79 return gpio;
80}
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000081#endif
82
Balaji T K14fa2dd2011-09-08 06:34:57 +000083#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
84static void omap4_vmmc_pbias_config(struct mmc *mmc)
85{
86 u32 value = 0;
Balaji T K14fa2dd2011-09-08 06:34:57 +000087
Lokesh Vutlac43c8332013-02-04 04:22:04 +000088 value = readl((*ctrl)->control_pbiaslite);
Balaji T K14fa2dd2011-09-08 06:34:57 +000089 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
Lokesh Vutlac43c8332013-02-04 04:22:04 +000090 writel(value, (*ctrl)->control_pbiaslite);
Balaji T K14fa2dd2011-09-08 06:34:57 +000091 /* set VMMC to 3V */
92 twl6030_power_mmc_init();
Lokesh Vutlac43c8332013-02-04 04:22:04 +000093 value = readl((*ctrl)->control_pbiaslite);
Balaji T K14fa2dd2011-09-08 06:34:57 +000094 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
Lokesh Vutlac43c8332013-02-04 04:22:04 +000095 writel(value, (*ctrl)->control_pbiaslite);
Balaji T K14fa2dd2011-09-08 06:34:57 +000096}
97#endif
98
Nishanth Menoncb199102013-03-26 05:20:54 +000099#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
Balaji T Kdd23e592012-03-12 02:25:49 +0000100static void omap5_pbias_config(struct mmc *mmc)
101{
102 u32 value = 0;
Balaji T Kdd23e592012-03-12 02:25:49 +0000103
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000104 value = readl((*ctrl)->control_pbias);
Balaji T Ka5d439c2013-06-06 05:04:32 +0000105 value &= ~SDCARD_PWRDNZ;
106 writel(value, (*ctrl)->control_pbias);
107 udelay(10); /* wait 10 us */
108 value &= ~SDCARD_BIAS_PWRDNZ;
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000109 writel(value, (*ctrl)->control_pbias);
Balaji T Kdd23e592012-03-12 02:25:49 +0000110
Nishanth Menon384bcae2013-03-26 05:20:56 +0000111 palmas_mmc1_poweron_ldo();
Balaji T Kdd23e592012-03-12 02:25:49 +0000112
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000113 value = readl((*ctrl)->control_pbias);
Balaji T Ka5d439c2013-06-06 05:04:32 +0000114 value |= SDCARD_BIAS_PWRDNZ;
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000115 writel(value, (*ctrl)->control_pbias);
Balaji T Ka5d439c2013-06-06 05:04:32 +0000116 udelay(150); /* wait 150 us */
117 value |= SDCARD_PWRDNZ;
118 writel(value, (*ctrl)->control_pbias);
119 udelay(150); /* wait 150 us */
Balaji T Kdd23e592012-03-12 02:25:49 +0000120}
121#endif
122
Balaji T K14fa2dd2011-09-08 06:34:57 +0000123unsigned char mmc_board_init(struct mmc *mmc)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700124{
Sukumar Ghoraide941242010-09-18 20:32:33 -0700125#if defined(CONFIG_OMAP34XX)
126 t2_t *t2_base = (t2_t *)T2_BASE;
127 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
Grazvydas Ignotasb1e725f2012-03-19 03:50:53 +0000128 u32 pbias_lite;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700129
Grazvydas Ignotasb1e725f2012-03-19 03:50:53 +0000130 pbias_lite = readl(&t2_base->pbias_lite);
131 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
132 writel(pbias_lite, &t2_base->pbias_lite);
133#endif
134#if defined(CONFIG_TWL4030_POWER)
135 twl4030_power_mmc_init();
136 mdelay(100); /* ramp-up delay from Linux code */
137#endif
138#if defined(CONFIG_OMAP34XX)
139 writel(pbias_lite | PBIASLITEPWRDNZ1 |
Sukumar Ghoraide941242010-09-18 20:32:33 -0700140 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
141 &t2_base->pbias_lite);
142
143 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
144 &t2_base->devconf0);
145
146 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
147 &t2_base->devconf1);
148
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000149 /* Change from default of 52MHz to 26MHz if necessary */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200150 if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000151 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
152 &t2_base->ctl_prog_io1);
153
Sukumar Ghoraide941242010-09-18 20:32:33 -0700154 writel(readl(&prcm_base->fclken1_core) |
155 EN_MMC1 | EN_MMC2 | EN_MMC3,
156 &prcm_base->fclken1_core);
157
158 writel(readl(&prcm_base->iclken1_core) |
159 EN_MMC1 | EN_MMC2 | EN_MMC3,
160 &prcm_base->iclken1_core);
161#endif
162
Balaji T K14fa2dd2011-09-08 06:34:57 +0000163#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
164 /* PBIAS config needed for MMC1 only */
165 if (mmc->block_dev.dev == 0)
166 omap4_vmmc_pbias_config(mmc);
167#endif
Nishanth Menoncb199102013-03-26 05:20:54 +0000168#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
Balaji T Kdd23e592012-03-12 02:25:49 +0000169 if (mmc->block_dev.dev == 0)
170 omap5_pbias_config(mmc);
171#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700172
173 return 0;
174}
175
Sricharan933efe62011-11-15 09:49:53 -0500176void mmc_init_stream(struct hsmmc *mmc_base)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700177{
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500178 ulong start;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700179
180 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
181
182 writel(MMC_CMD0, &mmc_base->cmd);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500183 start = get_timer(0);
184 while (!(readl(&mmc_base->stat) & CC_MASK)) {
185 if (get_timer(0) - start > MAX_RETRY_MS) {
186 printf("%s: timedout waiting for cc!\n", __func__);
187 return;
188 }
189 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700190 writel(CC_MASK, &mmc_base->stat)
191 ;
192 writel(MMC_CMD0, &mmc_base->cmd)
193 ;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500194 start = get_timer(0);
195 while (!(readl(&mmc_base->stat) & CC_MASK)) {
196 if (get_timer(0) - start > MAX_RETRY_MS) {
197 printf("%s: timedout waiting for cc2!\n", __func__);
198 return;
199 }
200 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700201 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
202}
203
204
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200205static int omap_hsmmc_init_setup(struct mmc *mmc)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700206{
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000207 struct hsmmc *mmc_base;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700208 unsigned int reg_val;
209 unsigned int dsor;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500210 ulong start;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700211
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000212 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
Balaji T K14fa2dd2011-09-08 06:34:57 +0000213 mmc_board_init(mmc);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700214
215 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
216 &mmc_base->sysconfig);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500217 start = get_timer(0);
218 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
219 if (get_timer(0) - start > MAX_RETRY_MS) {
220 printf("%s: timedout waiting for cc2!\n", __func__);
221 return TIMEOUT;
222 }
223 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700224 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500225 start = get_timer(0);
226 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
227 if (get_timer(0) - start > MAX_RETRY_MS) {
228 printf("%s: timedout waiting for softresetall!\n",
229 __func__);
230 return TIMEOUT;
231 }
232 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700233 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
234 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
235 &mmc_base->capa);
236
237 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
238
239 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
240 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
241 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
242
243 dsor = 240;
244 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
245 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
246 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
247 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500248 start = get_timer(0);
249 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
250 if (get_timer(0) - start > MAX_RETRY_MS) {
251 printf("%s: timedout waiting for ics!\n", __func__);
252 return TIMEOUT;
253 }
254 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700255 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
256
257 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
258
259 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
260 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
261 &mmc_base->ie);
262
263 mmc_init_stream(mmc_base);
264
265 return 0;
266}
267
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000268/*
269 * MMC controller internal finite state machine reset
270 *
271 * Used to reset command or data internal state machines, using respectively
272 * SRC or SRD bit of SYSCTL register
273 */
274static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
275{
276 ulong start;
277
278 mmc_reg_out(&mmc_base->sysctl, bit, bit);
279
Oleksandr Tyshchenko61a6cc22013-08-06 13:44:16 +0300280 /*
281 * CMD(DAT) lines reset procedures are slightly different
282 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
283 * According to OMAP3 TRM:
284 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
285 * returns to 0x0.
286 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
287 * procedure steps must be as follows:
288 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
289 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
290 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
291 * 3. Wait until the SRC (SRD) bit returns to 0x0
292 * (reset procedure is completed).
293 */
294#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
295 defined(CONFIG_AM33XX)
296 if (!(readl(&mmc_base->sysctl) & bit)) {
297 start = get_timer(0);
298 while (!(readl(&mmc_base->sysctl) & bit)) {
299 if (get_timer(0) - start > MAX_RETRY_MS)
300 return;
301 }
302 }
303#endif
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000304 start = get_timer(0);
305 while ((readl(&mmc_base->sysctl) & bit) != 0) {
306 if (get_timer(0) - start > MAX_RETRY_MS) {
307 printf("%s: timedout waiting for sysctl %x to clear\n",
308 __func__, bit);
309 return;
310 }
311 }
312}
Sukumar Ghoraide941242010-09-18 20:32:33 -0700313
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200314static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
Sukumar Ghoraide941242010-09-18 20:32:33 -0700315 struct mmc_data *data)
316{
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000317 struct hsmmc *mmc_base;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700318 unsigned int flags, mmc_stat;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500319 ulong start;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700320
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000321 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500322 start = get_timer(0);
Tom Rinia7778f82012-01-30 11:22:25 +0000323 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500324 if (get_timer(0) - start > MAX_RETRY_MS) {
Tom Rinia7778f82012-01-30 11:22:25 +0000325 printf("%s: timedout waiting on cmd inhibit to clear\n",
326 __func__);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500327 return TIMEOUT;
328 }
329 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700330 writel(0xFFFFFFFF, &mmc_base->stat);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500331 start = get_timer(0);
332 while (readl(&mmc_base->stat)) {
333 if (get_timer(0) - start > MAX_RETRY_MS) {
Grazvydas Ignotas15ceb1d2012-03-19 12:11:43 +0000334 printf("%s: timedout waiting for STAT (%x) to clear\n",
335 __func__, readl(&mmc_base->stat));
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500336 return TIMEOUT;
337 }
338 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700339 /*
340 * CMDREG
341 * CMDIDX[13:8] : Command index
342 * DATAPRNT[5] : Data Present Select
343 * ENCMDIDX[4] : Command Index Check Enable
344 * ENCMDCRC[3] : Command CRC Check Enable
345 * RSPTYP[1:0]
346 * 00 = No Response
347 * 01 = Length 136
348 * 10 = Length 48
349 * 11 = Length 48 Check busy after response
350 */
351 /* Delay added before checking the status of frq change
352 * retry not supported by mmc.c(core file)
353 */
354 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
355 udelay(50000); /* wait 50 ms */
356
357 if (!(cmd->resp_type & MMC_RSP_PRESENT))
358 flags = 0;
359 else if (cmd->resp_type & MMC_RSP_136)
360 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
361 else if (cmd->resp_type & MMC_RSP_BUSY)
362 flags = RSP_TYPE_LGHT48B;
363 else
364 flags = RSP_TYPE_LGHT48;
365
366 /* enable default flags */
367 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
368 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
369
370 if (cmd->resp_type & MMC_RSP_CRC)
371 flags |= CCCE_CHECK;
372 if (cmd->resp_type & MMC_RSP_OPCODE)
373 flags |= CICE_CHECK;
374
375 if (data) {
376 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
377 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
378 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
379 data->blocksize = 512;
380 writel(data->blocksize | (data->blocks << 16),
381 &mmc_base->blk);
382 } else
383 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
384
385 if (data->flags & MMC_DATA_READ)
386 flags |= (DP_DATA | DDIR_READ);
387 else
388 flags |= (DP_DATA | DDIR_WRITE);
389 }
390
391 writel(cmd->cmdarg, &mmc_base->arg);
Lubomir Popov152ba362013-08-14 18:59:18 +0300392 udelay(20); /* To fix "No status update" error on eMMC */
Sukumar Ghoraide941242010-09-18 20:32:33 -0700393 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
394
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500395 start = get_timer(0);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700396 do {
397 mmc_stat = readl(&mmc_base->stat);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500398 if (get_timer(0) - start > MAX_RETRY_MS) {
399 printf("%s : timeout: No status update\n", __func__);
400 return TIMEOUT;
401 }
402 } while (!mmc_stat);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700403
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000404 if ((mmc_stat & IE_CTO) != 0) {
405 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700406 return TIMEOUT;
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000407 } else if ((mmc_stat & ERRI_MASK) != 0)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700408 return -1;
409
410 if (mmc_stat & CC_MASK) {
411 writel(CC_MASK, &mmc_base->stat);
412 if (cmd->resp_type & MMC_RSP_PRESENT) {
413 if (cmd->resp_type & MMC_RSP_136) {
414 /* response type 2 */
415 cmd->response[3] = readl(&mmc_base->rsp10);
416 cmd->response[2] = readl(&mmc_base->rsp32);
417 cmd->response[1] = readl(&mmc_base->rsp54);
418 cmd->response[0] = readl(&mmc_base->rsp76);
419 } else
420 /* response types 1, 1b, 3, 4, 5, 6 */
421 cmd->response[0] = readl(&mmc_base->rsp10);
422 }
423 }
424
425 if (data && (data->flags & MMC_DATA_READ)) {
426 mmc_read_data(mmc_base, data->dest,
427 data->blocksize * data->blocks);
428 } else if (data && (data->flags & MMC_DATA_WRITE)) {
429 mmc_write_data(mmc_base, data->src,
430 data->blocksize * data->blocks);
431 }
432 return 0;
433}
434
Sricharan933efe62011-11-15 09:49:53 -0500435static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700436{
437 unsigned int *output_buf = (unsigned int *)buf;
438 unsigned int mmc_stat;
439 unsigned int count;
440
441 /*
442 * Start Polled Read
443 */
444 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
445 count /= 4;
446
447 while (size) {
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500448 ulong start = get_timer(0);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700449 do {
450 mmc_stat = readl(&mmc_base->stat);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500451 if (get_timer(0) - start > MAX_RETRY_MS) {
452 printf("%s: timedout waiting for status!\n",
453 __func__);
454 return TIMEOUT;
455 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700456 } while (mmc_stat == 0);
457
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000458 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
459 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
460
Sukumar Ghoraide941242010-09-18 20:32:33 -0700461 if ((mmc_stat & ERRI_MASK) != 0)
462 return 1;
463
464 if (mmc_stat & BRR_MASK) {
465 unsigned int k;
466
467 writel(readl(&mmc_base->stat) | BRR_MASK,
468 &mmc_base->stat);
469 for (k = 0; k < count; k++) {
470 *output_buf = readl(&mmc_base->data);
471 output_buf++;
472 }
473 size -= (count*4);
474 }
475
476 if (mmc_stat & BWR_MASK)
477 writel(readl(&mmc_base->stat) | BWR_MASK,
478 &mmc_base->stat);
479
480 if (mmc_stat & TC_MASK) {
481 writel(readl(&mmc_base->stat) | TC_MASK,
482 &mmc_base->stat);
483 break;
484 }
485 }
486 return 0;
487}
488
Sricharan933efe62011-11-15 09:49:53 -0500489static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
490 unsigned int size)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700491{
492 unsigned int *input_buf = (unsigned int *)buf;
493 unsigned int mmc_stat;
494 unsigned int count;
495
496 /*
Lubomir Popov152ba362013-08-14 18:59:18 +0300497 * Start Polled Write
Sukumar Ghoraide941242010-09-18 20:32:33 -0700498 */
499 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
500 count /= 4;
501
502 while (size) {
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500503 ulong start = get_timer(0);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700504 do {
505 mmc_stat = readl(&mmc_base->stat);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500506 if (get_timer(0) - start > MAX_RETRY_MS) {
507 printf("%s: timedout waiting for status!\n",
508 __func__);
509 return TIMEOUT;
510 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700511 } while (mmc_stat == 0);
512
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000513 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
514 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
515
Sukumar Ghoraide941242010-09-18 20:32:33 -0700516 if ((mmc_stat & ERRI_MASK) != 0)
517 return 1;
518
519 if (mmc_stat & BWR_MASK) {
520 unsigned int k;
521
522 writel(readl(&mmc_base->stat) | BWR_MASK,
523 &mmc_base->stat);
524 for (k = 0; k < count; k++) {
525 writel(*input_buf, &mmc_base->data);
526 input_buf++;
527 }
528 size -= (count*4);
529 }
530
531 if (mmc_stat & BRR_MASK)
532 writel(readl(&mmc_base->stat) | BRR_MASK,
533 &mmc_base->stat);
534
535 if (mmc_stat & TC_MASK) {
536 writel(readl(&mmc_base->stat) | TC_MASK,
537 &mmc_base->stat);
538 break;
539 }
540 }
541 return 0;
542}
543
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200544static void omap_hsmmc_set_ios(struct mmc *mmc)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700545{
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000546 struct hsmmc *mmc_base;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700547 unsigned int dsor = 0;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500548 ulong start;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700549
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000550 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700551 /* configue bus width */
552 switch (mmc->bus_width) {
553 case 8:
554 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
555 &mmc_base->con);
556 break;
557
558 case 4:
559 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
560 &mmc_base->con);
561 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
562 &mmc_base->hctl);
563 break;
564
565 case 1:
566 default:
567 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
568 &mmc_base->con);
569 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
570 &mmc_base->hctl);
571 break;
572 }
573
574 /* configure clock with 96Mhz system clock.
575 */
576 if (mmc->clock != 0) {
577 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
578 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
579 dsor++;
580 }
581
582 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
583 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
584
585 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
586 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
587
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500588 start = get_timer(0);
589 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
590 if (get_timer(0) - start > MAX_RETRY_MS) {
591 printf("%s: timedout waiting for ics!\n", __func__);
592 return;
593 }
594 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700595 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
596}
597
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200598#ifdef OMAP_HSMMC_USE_GPIO
599static int omap_hsmmc_getcd(struct mmc *mmc)
600{
601 struct omap_hsmmc_data *priv_data = mmc->priv;
602 int cd_gpio;
603
604 /* if no CD return as 1 */
605 cd_gpio = priv_data->cd_gpio;
606 if (cd_gpio < 0)
607 return 1;
608
609 return gpio_get_value(cd_gpio);
610}
611
612static int omap_hsmmc_getwp(struct mmc *mmc)
613{
614 struct omap_hsmmc_data *priv_data = mmc->priv;
615 int wp_gpio;
616
617 /* if no WP return as 0 */
618 wp_gpio = priv_data->wp_gpio;
619 if (wp_gpio < 0)
620 return 0;
621
622 return gpio_get_value(wp_gpio);
623}
624#endif
625
626static const struct mmc_ops omap_hsmmc_ops = {
627 .send_cmd = omap_hsmmc_send_cmd,
628 .set_ios = omap_hsmmc_set_ios,
629 .init = omap_hsmmc_init_setup,
630#ifdef OMAP_HSMMC_USE_GPIO
631 .getcd = omap_hsmmc_getcd,
632 .getwp = omap_hsmmc_getwp,
633#endif
634};
635
Nikita Kiryanove3913f52012-12-03 02:19:47 +0000636int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
637 int wp_gpio)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700638{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200639 struct mmc *mmc;
640 struct omap_hsmmc_data *priv_data;
641 struct mmc_config *cfg;
642 uint host_caps_val;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700643
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200644 priv_data = malloc(sizeof(*priv_data));
645 if (priv_data == NULL)
646 return -1;
647
648 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
649 MMC_MODE_HC;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700650
651 switch (dev_index) {
652 case 0:
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000653 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700654 break;
Tom Rini1037d582011-10-12 06:20:50 +0000655#ifdef OMAP_HSMMC2_BASE
Sukumar Ghoraide941242010-09-18 20:32:33 -0700656 case 1:
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000657 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
Lubomir Popov152ba362013-08-14 18:59:18 +0300658#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
659 defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT)
660 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
661 host_caps_val |= MMC_MODE_8BIT;
662#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700663 break;
Tom Rini1037d582011-10-12 06:20:50 +0000664#endif
665#ifdef OMAP_HSMMC3_BASE
Sukumar Ghoraide941242010-09-18 20:32:33 -0700666 case 2:
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000667 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
Lubomir Popov152ba362013-08-14 18:59:18 +0300668#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
669 /* Enable 8-bit interface for eMMC on DRA7XX */
670 host_caps_val |= MMC_MODE_8BIT;
671#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700672 break;
Tom Rini1037d582011-10-12 06:20:50 +0000673#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700674 default:
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000675 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700676 return 1;
677 }
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200678#ifdef OMAP_HSMMC_USE_GPIO
679 /* on error gpio values are set to -1, which is what we want */
Nikita Kiryanove874d5b2012-12-03 02:19:44 +0000680 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
Nikita Kiryanove3913f52012-12-03 02:19:47 +0000681 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200682#endif
Peter Korsgaard173ddc52013-03-21 04:00:04 +0000683
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200684 cfg = &priv_data->cfg;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700685
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200686 cfg->name = "OMAP SD/MMC";
687 cfg->ops = &omap_hsmmc_ops;
688
689 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
690 cfg->host_caps = host_caps_val & ~host_caps_mask;
691
692 cfg->f_min = 400000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000693
694 if (f_max != 0)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200695 cfg->f_max = f_max;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000696 else {
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200697 if (cfg->host_caps & MMC_MODE_HS) {
698 if (cfg->host_caps & MMC_MODE_HS_52MHz)
699 cfg->f_max = 52000000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000700 else
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200701 cfg->f_max = 26000000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000702 } else
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200703 cfg->f_max = 20000000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000704 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700705
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200706 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
John Rigby8feafcc2011-04-18 05:50:08 +0000707
John Rigby4ca92442011-04-19 05:48:14 +0000708#if defined(CONFIG_OMAP34XX)
709 /*
710 * Silicon revs 2.1 and older do not support multiblock transfers.
711 */
712 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200713 cfg->b_max = 1;
John Rigby4ca92442011-04-19 05:48:14 +0000714#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200715 mmc = mmc_create(cfg, priv_data);
716 if (mmc == NULL)
717 return -1;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700718
719 return 0;
720}