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Mathieu J. Poirier84dee302012-08-03 11:05:12 +00001/*
2 * Copyright (C) ST-Ericsson SA 2009
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#include <config.h>
20#include <common.h>
21#include <malloc.h>
22#include <i2c.h>
23#include <mmc.h>
24#include <asm/types.h>
25#include <asm/io.h>
26#include <asm/errno.h>
27#include <asm/arch/db8500_pincfg.h>
Mathieu J. Poirierb95f9ec2012-07-31 08:59:28 +000028#include <asm/arch/prcmu.h>
29#include <asm/arch/hardware.h>
Mathieu J. Poirier75dfe962012-07-31 08:59:30 +000030#include <asm/arch/sys_proto.h>
Mathieu J. Poirier84dee302012-08-03 11:05:12 +000031
John Rigby10ed93d2012-07-31 08:59:31 +000032#ifdef CONFIG_MMC
33#include "../../../drivers/mmc/arm_pl180_mmci.h"
34#endif
Mathieu J. Poirier84dee302012-08-03 11:05:12 +000035#include "db8500_pins.h"
36
37/*
38 * Get a global data pointer
39 */
40DECLARE_GLOBAL_DATA_PTR;
41
42/*
43 * Memory controller register
44 */
45#define DMC_BASE_ADDR 0x80156000
46#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
47
48/*
49 * GPIO pin config common for MOP500/HREF boards
50 */
51unsigned long gpio_cfg_common[] = {
52 /* I2C */
53 GPIO147_I2C0_SCL,
54 GPIO148_I2C0_SDA,
55 GPIO16_I2C1_SCL,
56 GPIO17_I2C1_SDA,
57 GPIO10_I2C2_SDA,
58 GPIO11_I2C2_SCL,
59 GPIO229_I2C3_SDA,
60 GPIO230_I2C3_SCL,
61
62 /* SSP0, to AB8500 */
63 GPIO143_SSP0_CLK,
64 GPIO144_SSP0_FRM,
65 GPIO145_SSP0_RXD | PIN_PULL_DOWN,
66 GPIO146_SSP0_TXD,
67
68 /* MMC0 (MicroSD card) */
69 GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
70 GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
71 GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
72 GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
73 GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
74 GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
75 GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
76 GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
77 GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
78 GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
79 GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
80
81 /* MMC4 (On-board eMMC) */
82 GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
83 GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
84 GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
85 GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
86 GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
87 GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
88 GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
89 GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
90 GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
91 GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
92 GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
93
94 /* UART2, console */
95 GPIO29_U2_RXD | PIN_INPUT_PULLUP,
96 GPIO30_U2_TXD | PIN_OUTPUT_HIGH,
97 GPIO31_U2_CTSn | PIN_INPUT_PULLUP,
98 GPIO32_U2_RTSn | PIN_OUTPUT_HIGH,
99
100 /*
101 * USB, pin 256-267 USB, Is probably already setup correctly from
102 * BootROM/boot stages, but we don't trust that and set it up anyway
103 */
104 GPIO256_USB_NXT,
105 GPIO257_USB_STP,
106 GPIO258_USB_XCLK,
107 GPIO259_USB_DIR,
108 GPIO260_USB_DAT7,
109 GPIO261_USB_DAT6,
110 GPIO262_USB_DAT5,
111 GPIO263_USB_DAT4,
112 GPIO264_USB_DAT3,
113 GPIO265_USB_DAT2,
114 GPIO266_USB_DAT1,
115 GPIO267_USB_DAT0,
116};
117
118unsigned long gpio_cfg_snowball[] = {
119 /* MMC0 (MicroSD card) */
120 GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */
121 GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */
122 GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */
123
124 /* eMMC */
125 GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */
126
127 /* LAN */
128 GPIO131_SM_ADQ8,
129 GPIO132_SM_ADQ9,
130 GPIO133_SM_ADQ10,
131 GPIO134_SM_ADQ11,
132 GPIO135_SM_ADQ12,
133 GPIO136_SM_ADQ13,
134 GPIO137_SM_ADQ14,
135 GPIO138_SM_ADQ15,
136
137 /* RSTn_LAN */
138 GPIO141_GPIO | PIN_OUTPUT_HIGH,
139};
140
141/*
142 * Miscellaneous platform dependent initialisations
143 */
144
145int board_init(void)
146{
147 /*
148 * Setup board (bd) and board-info (bi).
149 * bi_arch_number: Unique id for this board. It will passed in r1 to
150 * Linux startup code and is the machine_id.
151 * bi_boot_params: Where this board expects params.
152 */
153 gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL;
154 gd->bd->bi_boot_params = 0x00000100;
155
156 /* Configure GPIO pins needed by U-boot */
157 db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common));
158
159 db8500_gpio_config_pins(gpio_cfg_snowball,
160 ARRAY_SIZE(gpio_cfg_snowball));
161
162 return 0;
163}
164
165int dram_init(void)
166{
167 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
168 gd->ram_size = gd->bd->bi_dram[0].size =
169 get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
170
171 return 0;
172}
Mathieu J. Poirierb95f9ec2012-07-31 08:59:28 +0000173
174static int raise_ab8500_gpio16(void)
175{
176 int ret;
177
178 /* selection */
179 ret = ab8500_read(AB8500_MISC, AB8500_GPIO_SEL2_REG);
180 if (ret < 0)
181 goto out;
182
183 ret |= 0x80;
184 ret = ab8500_write(AB8500_MISC, AB8500_GPIO_SEL2_REG, ret);
185 if (ret < 0)
186 goto out;
187
188 /* direction */
189 ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR2_REG);
190 if (ret < 0)
191 goto out;
192
193 ret |= 0x80;
194 ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR2_REG, ret);
195 if (ret < 0)
196 goto out;
197
198 /* out */
199 ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT2_REG);
200 if (ret < 0)
201 goto out;
202
203 ret |= 0x80;
204 ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT2_REG, ret);
205
206out:
207 return ret;
208}
209
210static int raise_ab8500_gpio26(void)
211{
212 int ret;
213
214 /* selection */
215 ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR4_REG);
216 if (ret < 0)
217 goto out;
218
219 ret |= 0x2;
220 ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR4_REG, ret);
221 if (ret < 0)
222 goto out;
223
224 /* out */
225 ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT4_REG);
226 if (ret < 0)
227 goto out;
228
229 ret |= 0x2;
230 ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT4_REG, ret);
231
232out:
233 return ret;
234}
235
236int board_late_init(void)
237{
238 /* enable 3V3 for LAN controller */
239 if (raise_ab8500_gpio26() >= 0) {
240 /* Turn on FSMC device */
241 writel(0x1, 0x8000f000);
242 writel(0x1, 0x8000f008);
243
244 /* setup FSMC for LAN controler */
245 writel(0x305b, 0x80000000);
246
247 /* run at the highest possible speed */
248 writel(0x01010210, 0x80000004);
249 } else
250 printf("error: can't raise GPIO26\n");
251
252 /* enable 3v6 for GBF chip */
253 if ((raise_ab8500_gpio16() < 0))
254 printf("error: cant' raise GPIO16\n");
255
John Rigby10ed93d2012-07-31 08:59:31 +0000256 return 0;
257}
258
Mathieu J. Poirier75dfe962012-07-31 08:59:30 +0000259#ifdef CONFIG_MMC
John Rigby10ed93d2012-07-31 08:59:31 +0000260/*
261 * emmc_host_init - initialize the emmc controller.
262 * Configure GPIO settings, set initial clock and power for emmc slot.
263 * Initialize mmc struct and register with mmc framework.
264 */
265static int emmc_host_init(void)
266{
267 struct pl180_mmc_host *host;
268
269 host = malloc(sizeof(struct pl180_mmc_host));
270 if (!host)
271 return -ENOMEM;
272 memset(host, 0, sizeof(*host));
273
274 host->base = (struct sdi_registers *)CFG_EMMC_BASE;
275 host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
276 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 |
277 SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN;
278 strcpy(host->name, "EMMC");
279 host->caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
280 host->voltages = VOLTAGE_WINDOW_MMC;
281 host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
282 host->clock_max = ARM_MCLK / 2;
283 host->clock_in = ARM_MCLK;
284 host->version2 = 1;
285
286 return arm_pl180_mmci_init(host);
287}
288
289/*
290 * mmc_host_init - initialize the external mmc controller.
291 * Configure GPIO settings, set initial clock and power for mmc slot.
292 * Initialize mmc struct and register with mmc framework.
293 */
294static int mmc_host_init(void)
295{
296 struct pl180_mmc_host *host;
297 u32 sdi_u32;
298
299 host = malloc(sizeof(struct pl180_mmc_host));
300 if (!host)
301 return -ENOMEM;
302 memset(host, 0, sizeof(*host));
303
304 host->base = (struct sdi_registers *)CFG_MMC_BASE;
305 sdi_u32 = 0xBF;
306 writel(sdi_u32, &host->base->power);
307 host->pwr_init = 0xBF;
308 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 |
309 SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN;
310 strcpy(host->name, "MMC");
311 host->caps = MMC_MODE_8BIT;
312 host->b_max = 0;
313 host->voltages = VOLTAGE_WINDOW_SD;
314 host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
315 host->clock_max = ARM_MCLK / 2;
316 host->clock_in = ARM_MCLK;
317 host->version2 = 1;
318
319 return arm_pl180_mmci_init(host);
320}
321
322/*
323 * board_mmc_init - initialize all the mmc/sd host controllers.
324 * Called by generic mmc framework.
325 */
326int board_mmc_init(bd_t *bis)
327{
328 int error;
329
330 (void) bis;
331
332 error = emmc_host_init();
333 if (error) {
334 printf("emmc_host_init() %d\n", error);
335 return -1;
336 }
337
Mathieu J. Poirier75dfe962012-07-31 08:59:30 +0000338 u8500_mmc_power_init();
John Rigby10ed93d2012-07-31 08:59:31 +0000339
340 error = mmc_host_init();
341 if (error) {
342 printf("mmc_host_init() %d\n", error);
343 return -1;
344 }
Mathieu J. Poirier75dfe962012-07-31 08:59:30 +0000345
Mathieu J. Poirierb95f9ec2012-07-31 08:59:28 +0000346 return 0;
347}
John Rigby10ed93d2012-07-31 08:59:31 +0000348#endif /* CONFIG_MMC */