blob: 6f36dd417a93f5ba6dff58192446512af79f0af4 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ashish Kumare84a3242017-08-31 16:12:54 +05302/*
Priyanka Singh4238e372020-01-22 10:32:34 +00003 * Copyright 2017, 2020 NXP
Ashish Kumare84a3242017-08-31 16:12:54 +05304 */
5
6#ifndef __LS1088A_RDB_H
7#define __LS1088A_RDB_H
8
9#include "ls1088a_common.h"
10
Pankit Garg143af3c2018-12-27 04:37:55 +000011#if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Sumit Garg10e7eaf2018-01-06 09:04:24 +053013#ifndef CONFIG_SPL_BUILD
Ashish Kumare84a3242017-08-31 16:12:54 +053014#define CONFIG_QIXIS_I2C_ACCESS
Sumit Garg10e7eaf2018-01-06 09:04:24 +053015#endif
Ashish Kumare84a3242017-08-31 16:12:54 +053016#define SYS_NO_FLASH
Ashish Kumare84a3242017-08-31 16:12:54 +053017#endif
18
19#define CONFIG_SYS_CLK_FREQ 100000000
20#define CONFIG_DDR_CLK_FREQ 100000000
21#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
22#define COUNTER_FREQUENCY 25000000 /* 25MHz */
23
24#define CONFIG_DDR_SPD
25#ifdef CONFIG_EMU
26#define CONFIG_SYS_FSL_DDR_EMU
27#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
28#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
29#else
30#define CONFIG_DDR_ECC
31#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
32#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
33#endif
34#define SPD_EEPROM_ADDRESS 0x51
35#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
36#define CONFIG_DIMM_SLOTS_PER_CTLR 1
37
38
39#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
40#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
41#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
42#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
43
44#define CONFIG_SYS_NOR0_CSPR \
45 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
46 CSPR_PORT_SIZE_16 | \
47 CSPR_MSEL_NOR | \
48 CSPR_V)
49#define CONFIG_SYS_NOR0_CSPR_EARLY \
50 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
51 CSPR_PORT_SIZE_16 | \
52 CSPR_MSEL_NOR | \
53 CSPR_V)
54#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
55#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
56 FTIM0_NOR_TEADC(0x1) | \
57 FTIM0_NOR_TEAHC(0x1))
58#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
59 FTIM1_NOR_TRAD_NOR(0x1))
60#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
61 FTIM2_NOR_TCH(0x0) | \
62 FTIM2_NOR_TWP(0x1))
63#define CONFIG_SYS_NOR_FTIM3 0x04000000
64#define CONFIG_SYS_IFC_CCR 0x01000000
65
66#ifndef SYS_NO_FLASH
Ashish Kumare84a3242017-08-31 16:12:54 +053067#define CONFIG_SYS_FLASH_QUIET_TEST
68#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
69
70#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
71#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
72#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
73#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
74
75#define CONFIG_SYS_FLASH_EMPTY_INFO
76#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
77#endif
78#endif
Sumit Garg10e7eaf2018-01-06 09:04:24 +053079
80#ifndef SPL_NO_IFC
Ashish Kumard798a6e2017-11-28 10:52:17 +053081#define CONFIG_NAND_FSL_IFC
Sumit Garg10e7eaf2018-01-06 09:04:24 +053082#endif
83
Ashish Kumare84a3242017-08-31 16:12:54 +053084#define CONFIG_SYS_NAND_MAX_ECCPOS 256
85#define CONFIG_SYS_NAND_MAX_OOBFREE 2
86
87#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
88#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
89 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
90 | CSPR_MSEL_NAND /* MSEL = NAND */ \
91 | CSPR_V)
92#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
93
94#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
95 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
96 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
97 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
98 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
99 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
100 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
101
102#define CONFIG_SYS_NAND_ONFI_DETECTION
103
104/* ONFI NAND Flash mode0 Timing Params */
105#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
106 FTIM0_NAND_TWP(0x18) | \
107 FTIM0_NAND_TWCHT(0x07) | \
108 FTIM0_NAND_TWH(0x0a))
109#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
110 FTIM1_NAND_TWBE(0x39) | \
111 FTIM1_NAND_TRR(0x0e) | \
112 FTIM1_NAND_TRP(0x18))
113#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
114 FTIM2_NAND_TREH(0x0a) | \
115 FTIM2_NAND_TWHRE(0x1e))
116#define CONFIG_SYS_NAND_FTIM3 0x0
117
118#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
119#define CONFIG_SYS_MAX_NAND_DEVICE 1
120#define CONFIG_MTD_NAND_VERIFY_WRITE
121
122#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
123
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530124#ifndef SPL_NO_QIXIS
Ashish Kumare84a3242017-08-31 16:12:54 +0530125#define CONFIG_FSL_QIXIS
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530126#endif
127
Ashish Kumare84a3242017-08-31 16:12:54 +0530128#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
Rajesh Bhagatef0789b2018-01-17 16:13:09 +0530129#define QIXIS_BRDCFG4_OFFSET 0x54
Ashish Kumare84a3242017-08-31 16:12:54 +0530130#define QIXIS_LBMAP_SWITCH 2
131#define QIXIS_QMAP_MASK 0xe0
132#define QIXIS_QMAP_SHIFT 5
133#define QIXIS_LBMAP_MASK 0x1f
134#define QIXIS_LBMAP_SHIFT 5
135#define QIXIS_LBMAP_DFLTBANK 0x00
136#define QIXIS_LBMAP_ALTBANK 0x20
137#define QIXIS_LBMAP_SD 0x00
Ashish Kumar6c8945e2018-01-17 12:16:37 +0530138#define QIXIS_LBMAP_EMMC 0x00
Ashish Kumare84a3242017-08-31 16:12:54 +0530139#define QIXIS_LBMAP_SD_QSPI 0x00
140#define QIXIS_LBMAP_QSPI 0x00
141#define QIXIS_RCW_SRC_SD 0x40
Ashish Kumar6c8945e2018-01-17 12:16:37 +0530142#define QIXIS_RCW_SRC_EMMC 0x41
Ashish Kumare84a3242017-08-31 16:12:54 +0530143#define QIXIS_RCW_SRC_QSPI 0x62
144#define QIXIS_RST_CTL_RESET 0x31
145#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
146#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
147#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
148#define QIXIS_RST_FORCE_MEM 0x01
149
150#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
151#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
152 | CSPR_PORT_SIZE_8 \
153 | CSPR_MSEL_GPCM \
154 | CSPR_V)
155#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
156 | CSPR_PORT_SIZE_8 \
157 | CSPR_MSEL_GPCM \
158 | CSPR_V)
159
160#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
161#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
162/* QIXIS Timing parameters*/
163#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
164 FTIM0_GPCM_TEADC(0x0e) | \
165 FTIM0_GPCM_TEAHC(0x0e))
166#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
167 FTIM1_GPCM_TRAD(0x3f))
168#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
169 FTIM2_GPCM_TCH(0xf) | \
170 FTIM2_GPCM_TWP(0x3E))
171#define SYS_FPGA_CS_FTIM3 0x0
172
Pankit Garg143af3c2018-12-27 04:37:55 +0000173#if defined(CONFIG_TFABOOT) || \
174 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Ashish Kumare84a3242017-08-31 16:12:54 +0530175#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
176#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
177#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
178#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
179#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
180#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
181#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
182#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
183#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
184#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
185#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
186#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
187#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
188#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
189#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
190#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
191#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
192#else
193#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
194#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
195#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
196#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
197#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
198#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
199#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
200#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
201#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
202#endif
203
Ashish Kumare84a3242017-08-31 16:12:54 +0530204#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
205
Stephen Carlsonb5ee48c2021-02-08 11:11:29 +0100206#define I2C_MUX_CH_VOL_MONITOR 0xA
Rajesh Bhagat23a12cb2018-01-17 16:13:05 +0530207/* Voltage monitor on channel 2*/
208#define I2C_VOL_MONITOR_ADDR 0x63
209#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
210#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
211#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
Rajesh Bhagatef0789b2018-01-17 16:13:09 +0530212#define I2C_SVDD_MONITOR_ADDR 0x4F
213
214#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
215#define CONFIG_VID
216
217/* The lowest and highest voltage allowed for LS1088ARDB */
218#define VDD_MV_MIN 819
219#define VDD_MV_MAX 1212
220
221#define CONFIG_VOL_MONITOR_LTC3882_SET
222#define CONFIG_VOL_MONITOR_LTC3882_READ
Rajesh Bhagat23a12cb2018-01-17 16:13:05 +0530223
Rajesh Bhagat23a12cb2018-01-17 16:13:05 +0530224#define PWM_CHANNEL0 0x0
225
Ashish Kumare84a3242017-08-31 16:12:54 +0530226/*
227 * I2C bus multiplexer
228 */
229#define I2C_MUX_PCA_ADDR_PRI 0x77
230#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
231#define I2C_RETIMER_ADDR 0x18
232#define I2C_MUX_CH_DEFAULT 0x8
233#define I2C_MUX_CH5 0xD
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530234
235#ifndef SPL_NO_RTC
Ashish Kumare84a3242017-08-31 16:12:54 +0530236/*
237* RTC configuration
238*/
239#define RTC
Ashish Kumare84a3242017-08-31 16:12:54 +0530240#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530241#endif
Ashish Kumare84a3242017-08-31 16:12:54 +0530242
243/* EEPROM */
244#define CONFIG_ID_EEPROM
245#define CONFIG_SYS_I2C_EEPROM_NXID
246#define CONFIG_SYS_EEPROM_BUS_NUM 0
247#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
248#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
249#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
250#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
251
Ashish Kumar099f4092017-11-06 13:18:43 +0530252#ifdef CONFIG_SPL_BUILD
253#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
254#else
Ashish Kumare84a3242017-08-31 16:12:54 +0530255#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Ashish Kumar099f4092017-11-06 13:18:43 +0530256#endif
Ashish Kumare84a3242017-08-31 16:12:54 +0530257
258#define CONFIG_FSL_MEMAC
259
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530260#ifndef SPL_NO_ENV
Ashish Kumare84a3242017-08-31 16:12:54 +0530261/* Initial environment variables */
Pankit Garg143af3c2018-12-27 04:37:55 +0000262#ifdef CONFIG_TFABOOT
263#define QSPI_MC_INIT_CMD \
264 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
265 "sf read 0x80100000 0xE00000 0x100000;" \
266 "env exists secureboot && " \
Priyanka Singh4238e372020-01-22 10:32:34 +0000267 "sf read 0x80640000 0x640000 0x40000 && " \
268 "sf read 0x80680000 0x680000 0x40000 && " \
269 "esbc_validate 0x80640000 && " \
270 "esbc_validate 0x80680000 ;" \
Pankit Garg143af3c2018-12-27 04:37:55 +0000271 "fsl_mc start mc 0x80000000 0x80100000\0"
272#define SD_MC_INIT_CMD \
273 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
274 "mmc read 0x80100000 0x7000 0x800;" \
275 "env exists secureboot && " \
Priyanka Singh4238e372020-01-22 10:32:34 +0000276 "mmc read 0x80640000 0x3200 0x20 && " \
277 "mmc read 0x80680000 0x3400 0x20 && " \
278 "esbc_validate 0x80640000 && " \
279 "esbc_validate 0x80680000 ;" \
Pankit Garg143af3c2018-12-27 04:37:55 +0000280 "fsl_mc start mc 0x80000000 0x80100000\0"
281#else
Ashish Kumare84a3242017-08-31 16:12:54 +0530282#if defined(CONFIG_QSPI_BOOT)
Ashish Kumard9195c62017-11-06 13:19:28 +0530283#define MC_INIT_CMD \
Ashish Kumare84a3242017-08-31 16:12:54 +0530284 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530285 "sf read 0x80100000 0xE00000 0x100000;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530286 "env exists secureboot && " \
Priyanka Singh4238e372020-01-22 10:32:34 +0000287 "sf read 0x80640000 0x640000 0x40000 && " \
288 "sf read 0x80680000 0x680000 0x40000 && " \
289 "esbc_validate 0x80640000 && " \
290 "esbc_validate 0x80680000 ;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530291 "fsl_mc start mc 0x80000000 0x80100000\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530292 "mcmemsize=0x70000000\0"
Ashish Kumar099f4092017-11-06 13:18:43 +0530293#elif defined(CONFIG_SD_BOOT)
Ashish Kumard9195c62017-11-06 13:19:28 +0530294#define MC_INIT_CMD \
295 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
296 "mmc read 0x80100000 0x7000 0x800;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530297 "env exists secureboot && " \
Priyanka Singh4238e372020-01-22 10:32:34 +0000298 "mmc read 0x80640000 0x3200 0x20 && " \
299 "mmc read 0x80680000 0x3400 0x20 && " \
300 "esbc_validate 0x80640000 && " \
301 "esbc_validate 0x80680000 ;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530302 "fsl_mc start mc 0x80000000 0x80100000\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530303 "mcmemsize=0x70000000\0"
304#endif
Pankit Garg143af3c2018-12-27 04:37:55 +0000305#endif /* CONFIG_TFABOOT */
Ashish Kumard9195c62017-11-06 13:19:28 +0530306
Ashish Kumar099f4092017-11-06 13:18:43 +0530307#undef CONFIG_EXTRA_ENV_SETTINGS
Pankit Garg143af3c2018-12-27 04:37:55 +0000308#ifdef CONFIG_TFABOOT
309#define CONFIG_EXTRA_ENV_SETTINGS \
310 "BOARD=ls1088ardb\0" \
311 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
312 "ramdisk_addr=0x800000\0" \
313 "ramdisk_size=0x2000000\0" \
314 "fdt_high=0xa0000000\0" \
315 "initrd_high=0xffffffffffffffff\0" \
316 "fdt_addr=0x64f00000\0" \
317 "kernel_addr=0x1000000\0" \
318 "kernel_addr_sd=0x8000\0" \
Priyanka Singh4238e372020-01-22 10:32:34 +0000319 "kernelhdr_addr_sd=0x3000\0" \
Pankit Garg143af3c2018-12-27 04:37:55 +0000320 "kernel_start=0x580100000\0" \
Priyanka Singh4238e372020-01-22 10:32:34 +0000321 "kernelheader_start=0x580600000\0" \
Pankit Garg143af3c2018-12-27 04:37:55 +0000322 "scriptaddr=0x80000000\0" \
323 "scripthdraddr=0x80080000\0" \
324 "fdtheader_addr_r=0x80100000\0" \
Priyanka Singh4238e372020-01-22 10:32:34 +0000325 "kernelheader_addr=0x600000\0" \
Pankit Garg143af3c2018-12-27 04:37:55 +0000326 "kernelheader_addr_r=0x80200000\0" \
327 "kernel_addr_r=0x81000000\0" \
328 "kernelheader_size=0x40000\0" \
329 "fdt_addr_r=0x90000000\0" \
330 "load_addr=0xa0000000\0" \
331 "kernel_size=0x2800000\0" \
332 "kernel_size_sd=0x14000\0" \
Udit Agarwald749bf92019-11-20 08:49:06 +0000333 "kernelhdr_size_sd=0x20\0" \
Pankit Garg143af3c2018-12-27 04:37:55 +0000334 QSPI_MC_INIT_CMD \
335 "mcmemsize=0x70000000\0" \
336 BOOTENV \
337 "boot_scripts=ls1088ardb_boot.scr\0" \
338 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
339 "scan_dev_for_boot_part=" \
340 "part list ${devtype} ${devnum} devplist; " \
341 "env exists devplist || setenv devplist 1; " \
342 "for distro_bootpart in ${devplist}; do " \
343 "if fstype ${devtype} " \
344 "${devnum}:${distro_bootpart} " \
345 "bootfstype; then " \
346 "run scan_dev_for_boot; " \
347 "fi; " \
348 "done\0" \
Pankit Garg143af3c2018-12-27 04:37:55 +0000349 "boot_a_script=" \
350 "load ${devtype} ${devnum}:${distro_bootpart} " \
351 "${scriptaddr} ${prefix}${script}; " \
352 "env exists secureboot && load ${devtype} " \
353 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai78c58082019-04-23 05:52:17 +0000354 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
355 "env exists secureboot " \
Pankit Garg143af3c2018-12-27 04:37:55 +0000356 "&& esbc_validate ${scripthdraddr};" \
357 "source ${scriptaddr}\0" \
358 "installer=load mmc 0:2 $load_addr " \
359 "/flex_installer_arm64.itb; " \
360 "env exists mcinitcmd && run mcinitcmd && " \
361 "mmc read 0x80001000 0x6800 0x800;" \
362 "fsl_mc lazyapply dpl 0x80001000;" \
363 "bootm $load_addr#ls1088ardb\0" \
364 "qspi_bootcmd=echo Trying load from qspi..;" \
365 "sf probe && sf read $load_addr " \
366 "$kernel_addr $kernel_size ; env exists secureboot " \
367 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
368 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
369 "bootm $load_addr#$BOARD\0" \
370 "sd_bootcmd=echo Trying load from sd card..;" \
371 "mmcinfo; mmc read $load_addr " \
372 "$kernel_addr_sd $kernel_size_sd ;" \
373 "env exists secureboot && mmc read $kernelheader_addr_r "\
374 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
375 " && esbc_validate ${kernelheader_addr_r};" \
376 "bootm $load_addr#$BOARD\0"
377#else
Ashish Kumar099f4092017-11-06 13:18:43 +0530378#define CONFIG_EXTRA_ENV_SETTINGS \
Ashish Kumard9195c62017-11-06 13:19:28 +0530379 "BOARD=ls1088ardb\0" \
Ashish Kumar099f4092017-11-06 13:18:43 +0530380 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Ashish Kumar099f4092017-11-06 13:18:43 +0530381 "ramdisk_addr=0x800000\0" \
382 "ramdisk_size=0x2000000\0" \
383 "fdt_high=0xa0000000\0" \
384 "initrd_high=0xffffffffffffffff\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530385 "fdt_addr=0x64f00000\0" \
386 "kernel_addr=0x1000000\0" \
387 "kernel_addr_sd=0x8000\0" \
Priyanka Singh4238e372020-01-22 10:32:34 +0000388 "kernelhdr_addr_sd=0x3000\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530389 "kernel_start=0x580100000\0" \
390 "kernelheader_start=0x580800000\0" \
391 "scriptaddr=0x80000000\0" \
392 "scripthdraddr=0x80080000\0" \
393 "fdtheader_addr_r=0x80100000\0" \
Priyanka Singh4238e372020-01-22 10:32:34 +0000394 "kernelheader_addr=0x600000\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530395 "kernelheader_addr_r=0x80200000\0" \
396 "kernel_addr_r=0x81000000\0" \
397 "kernelheader_size=0x40000\0" \
398 "fdt_addr_r=0x90000000\0" \
399 "load_addr=0xa0000000\0" \
400 "kernel_size=0x2800000\0" \
401 "kernel_size_sd=0x14000\0" \
Udit Agarwald749bf92019-11-20 08:49:06 +0000402 "kernelhdr_size_sd=0x20\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530403 MC_INIT_CMD \
404 BOOTENV \
405 "boot_scripts=ls1088ardb_boot.scr\0" \
406 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
407 "scan_dev_for_boot_part=" \
408 "part list ${devtype} ${devnum} devplist; " \
409 "env exists devplist || setenv devplist 1; " \
410 "for distro_bootpart in ${devplist}; do " \
411 "if fstype ${devtype} " \
412 "${devnum}:${distro_bootpart} " \
413 "bootfstype; then " \
414 "run scan_dev_for_boot; " \
415 "fi; " \
416 "done\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530417 "boot_a_script=" \
418 "load ${devtype} ${devnum}:${distro_bootpart} " \
419 "${scriptaddr} ${prefix}${script}; " \
420 "env exists secureboot && load ${devtype} " \
421 "${devnum}:${distro_bootpart} " \
422 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
423 "&& esbc_validate ${scripthdraddr};" \
424 "source ${scriptaddr}\0" \
425 "installer=load mmc 0:2 $load_addr " \
426 "/flex_installer_arm64.itb; " \
427 "env exists mcinitcmd && run mcinitcmd && " \
Jagdish Gediyaf4ef4762018-06-05 09:04:05 +0530428 "mmc read 0x80001000 0x6800 0x800;" \
429 "fsl_mc lazyapply dpl 0x80001000;" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530430 "bootm $load_addr#ls1088ardb\0" \
431 "qspi_bootcmd=echo Trying load from qspi..;" \
432 "sf probe && sf read $load_addr " \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530433 "$kernel_addr $kernel_size ; env exists secureboot " \
434 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
435 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
Ashish Kumard9195c62017-11-06 13:19:28 +0530436 "bootm $load_addr#$BOARD\0" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530437 "sd_bootcmd=echo Trying load from sd card..;" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530438 "mmcinfo; mmc read $load_addr " \
439 "$kernel_addr_sd $kernel_size_sd ;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530440 "env exists secureboot && mmc read $kernelheader_addr_r "\
441 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
442 " && esbc_validate ${kernelheader_addr_r};" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530443 "bootm $load_addr#$BOARD\0"
Pankit Garg143af3c2018-12-27 04:37:55 +0000444#endif /* CONFIG_TFABOOT */
Ashish Kumare84a3242017-08-31 16:12:54 +0530445
Ashish Kumard9195c62017-11-06 13:19:28 +0530446#undef CONFIG_BOOTCOMMAND
Pankit Garg143af3c2018-12-27 04:37:55 +0000447#ifdef CONFIG_TFABOOT
448#define QSPI_NOR_BOOTCOMMAND \
Udit Agarwald749bf92019-11-20 08:49:06 +0000449 "sf read 0x80001000 0xd00000 0x100000;" \
Pankit Garg143af3c2018-12-27 04:37:55 +0000450 "env exists mcinitcmd && env exists secureboot " \
Priyanka Singh4238e372020-01-22 10:32:34 +0000451 " && sf read 0x806C0000 0x6C0000 0x100000 " \
452 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Pankit Garg143af3c2018-12-27 04:37:55 +0000453 "&& fsl_mc lazyapply dpl 0x80001000;" \
454 "run distro_bootcmd;run qspi_bootcmd;" \
455 "env exists secureboot && esbc_halt;"
456#define SD_BOOTCOMMAND \
457 "env exists mcinitcmd && mmcinfo; " \
458 "mmc read 0x80001000 0x6800 0x800; " \
459 "env exists mcinitcmd && env exists secureboot " \
Priyanka Singh4238e372020-01-22 10:32:34 +0000460 " && mmc read 0x806C0000 0x3600 0x20 " \
461 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Pankit Garg143af3c2018-12-27 04:37:55 +0000462 "&& fsl_mc lazyapply dpl 0x80001000;" \
463 "run distro_bootcmd;run sd_bootcmd;" \
464 "env exists secureboot && esbc_halt;"
465#else
Ashish Kumard9195c62017-11-06 13:19:28 +0530466#if defined(CONFIG_QSPI_BOOT)
467/* Try to boot an on-QSPI kernel first, then do normal distro boot */
468#define CONFIG_BOOTCOMMAND \
Jagdish Gediyaf4ef4762018-06-05 09:04:05 +0530469 "sf read 0x80001000 0xd00000 0x100000;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530470 "env exists mcinitcmd && env exists secureboot " \
Priyanka Singh4238e372020-01-22 10:32:34 +0000471 " && sf read 0x806C0000 0x6C0000 0x100000 " \
472 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Jagdish Gediyaf4ef4762018-06-05 09:04:05 +0530473 "&& fsl_mc lazyapply dpl 0x80001000;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530474 "run distro_bootcmd;run qspi_bootcmd;" \
475 "env exists secureboot && esbc_halt;"
476
Ashish Kumard9195c62017-11-06 13:19:28 +0530477/* Try to boot an on-SD kernel first, then do normal distro boot */
478#elif defined(CONFIG_SD_BOOT)
479#define CONFIG_BOOTCOMMAND \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530480 "env exists mcinitcmd && mmcinfo; " \
Jagdish Gediyaf4ef4762018-06-05 09:04:05 +0530481 "mmc read 0x80001000 0x6800 0x800; " \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530482 "env exists mcinitcmd && env exists secureboot " \
Priyanka Singh4238e372020-01-22 10:32:34 +0000483 " && mmc read 0x806C0000 0x3600 0x20 " \
484 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Jagdish Gediyaf4ef4762018-06-05 09:04:05 +0530485 "&& fsl_mc lazyapply dpl 0x80001000;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530486 "run distro_bootcmd;run sd_bootcmd;" \
487 "env exists secureboot && esbc_halt;"
Ashish Kumare84a3242017-08-31 16:12:54 +0530488#endif
Pankit Garg143af3c2018-12-27 04:37:55 +0000489#endif /* CONFIG_TFABOOT */
Ashish Kumare84a3242017-08-31 16:12:54 +0530490
491/* MAC/PHY configuration */
492#ifdef CONFIG_FSL_MC_ENET
Ashish Kumare84a3242017-08-31 16:12:54 +0530493#define AQ_PHY_ADDR1 0x00
494#define AQR105_IRQ_MASK 0x00000004
495
496#define QSGMII1_PORT1_PHY_ADDR 0x0c
497#define QSGMII1_PORT2_PHY_ADDR 0x0d
498#define QSGMII1_PORT3_PHY_ADDR 0x0e
499#define QSGMII1_PORT4_PHY_ADDR 0x0f
500#define QSGMII2_PORT1_PHY_ADDR 0x1c
501#define QSGMII2_PORT2_PHY_ADDR 0x1d
502#define QSGMII2_PORT3_PHY_ADDR 0x1e
503#define QSGMII2_PORT4_PHY_ADDR 0x1f
504
Ashish Kumare84a3242017-08-31 16:12:54 +0530505#define CONFIG_ETHPRIME "DPMAC1@xgmii"
506#define CONFIG_PHY_GIGE
507#endif
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530508#endif
Ashish Kumare84a3242017-08-31 16:12:54 +0530509
510/* MMC */
511#ifdef CONFIG_MMC
Ashish Kumare84a3242017-08-31 16:12:54 +0530512#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
513#endif
514
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530515#ifndef SPL_NO_ENV
Ashish Kumare84a3242017-08-31 16:12:54 +0530516
517#define BOOT_TARGET_DEVICES(func) \
Ashish Kumare84a3242017-08-31 16:12:54 +0530518 func(MMC, mmc, 0) \
Era Tiwarie08bcc02020-05-15 12:48:39 +0530519 func(USB, usb, 0) \
Mian Yousaf Kaukab080c9512019-01-29 16:38:32 +0100520 func(SCSI, scsi, 0) \
521 func(DHCP, dhcp, na)
Ashish Kumare84a3242017-08-31 16:12:54 +0530522#include <config_distro_bootcmd.h>
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530523#endif
Ashish Kumare84a3242017-08-31 16:12:54 +0530524
525#include <asm/fsl_secure_boot.h>
526
527#endif /* __LS1088A_RDB_H */