blob: e0435cc0a7a7429c88a394031c81de36868f3b13 [file] [log] [blame]
York Sunf749db32014-06-23 15:15:56 -07001/*
2 * Copyright (C) 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS2_COMMON_H
8#define __LS2_COMMON_H
9
10#define CONFIG_SYS_GENERIC_BOARD
11
12#define CONFIG_REMAKE_ELF
13#define CONFIG_FSL_LSCH3
14#define CONFIG_LS2085A
15#define CONFIG_GICV3
Bhupesh Sharma9c66ce62015-01-06 13:11:21 -080016#define CONFIG_FSL_TZPC_BP147
York Sunf749db32014-06-23 15:15:56 -070017
Bhupesh Sharma1b1069c2015-01-23 15:50:05 +053018/* Errata fixes */
19#define CONFIG_ARM_ERRATA_828024
20#define CONFIG_ARM_ERRATA_826974
21
York Sunf749db32014-06-23 15:15:56 -070022/* Link Definitions */
York Sun8aeb8932014-09-08 12:20:02 -070023#define CONFIG_SYS_TEXT_BASE 0x30001000
York Sunf749db32014-06-23 15:15:56 -070024
Prabhakar Kushwahae211c122014-07-16 09:21:12 +053025#ifdef CONFIG_EMU
York Sunf749db32014-06-23 15:15:56 -070026#define CONFIG_SYS_NO_FLASH
Prabhakar Kushwahae211c122014-07-16 09:21:12 +053027#endif
York Sunf749db32014-06-23 15:15:56 -070028
29#define CONFIG_SUPPORT_RAW_INITRD
30
31#define CONFIG_SKIP_LOWLEVEL_INIT
32#define CONFIG_BOARD_EARLY_INIT_F 1
33
York Sunf749db32014-06-23 15:15:56 -070034/* Flat Device Tree Definitions */
35#define CONFIG_OF_LIBFDT
36#define CONFIG_OF_BOARD_SETUP
37
38/* new uImage format support */
39#define CONFIG_FIT
40#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
41
42#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
43#ifndef CONFIG_SYS_FSL_DDR4
44#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
45#define CONFIG_SYS_DDR_RAW_TIMING
46#endif
47#define CONFIG_DIMM_SLOTS_PER_CTLR 1
48#define CONFIG_CHIP_SELECTS_PER_CTRL 4
49
50#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
51
York Sunf749db32014-06-23 15:15:56 -070052#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
53#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
54#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
55#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
York Sund9c68b12014-08-13 10:21:05 -070056#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
57
York Sun8bfa3012014-09-08 12:20:01 -070058/*
59 * SMP Definitinos
60 */
61#define CPU_RELEASE_ADDR secondary_boot_func
62
York Sund9c68b12014-08-13 10:21:05 -070063#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
64#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
65/*
66 * DDR controller use 0 as the base address for binding.
67 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
68 */
69#define CONFIG_SYS_DP_DDR_BASE_PHY 0
70#define CONFIG_DP_DDR_CTRL 2
71#define CONFIG_DP_DDR_NUM_CTRLS 1
72#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
York Sunf749db32014-06-23 15:15:56 -070073
74/* Generic Timer Definitions */
75#define COUNTER_FREQUENCY 12000000 /* 12MHz */
76
77/* Size of malloc() pool */
78#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
79
80/* I2C */
81#define CONFIG_CMD_I2C
82#define CONFIG_SYS_I2C
83#define CONFIG_SYS_I2C_MXC
84#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
85#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
86
87/* Serial Port */
88#define CONFIG_CONS_INDEX 2
89#define CONFIG_SYS_NS16550
90#define CONFIG_SYS_NS16550_SERIAL
91#define CONFIG_SYS_NS16550_REG_SIZE 1
92#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
93
94#define CONFIG_BAUDRATE 115200
95#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
96
97/* IFC */
98#define CONFIG_FSL_IFC
99#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
100#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
101/*
102 * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
103 * address 0. But this region is limited to 256MB. To accommodate bigger NOR
104 * flash and other devices, we will map CS0 to 0x580000000 after relocation.
105 * CONFIG_SYS_FLASH_BASE has the final address (core view)
106 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
107 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
108 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
109 */
110#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
111#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
112#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
113
114/*
115 * NOR Flash Timing Params
116 */
117#define CONFIG_SYS_NOR0_CSPR \
118 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
119 CSPR_PORT_SIZE_16 | \
120 CSPR_MSEL_NOR | \
121 CSPR_V)
122#define CONFIG_SYS_NOR0_CSPR_EARLY \
123 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
124 CSPR_PORT_SIZE_16 | \
125 CSPR_MSEL_NOR | \
126 CSPR_V)
127#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
128#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
129 FTIM0_NOR_TEADC(0x1) | \
130 FTIM0_NOR_TEAHC(0x1))
131#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
132 FTIM1_NOR_TRAD_NOR(0x1))
133#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
134 FTIM2_NOR_TCH(0x0) | \
135 FTIM2_NOR_TWP(0x1))
136#define CONFIG_SYS_NOR_FTIM3 0x04000000
137#define CONFIG_SYS_IFC_CCR 0x01000000
138
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530139#ifndef CONFIG_SYS_NO_FLASH
140#define CONFIG_FLASH_CFI_DRIVER
141#define CONFIG_SYS_FLASH_CFI
142#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
143#define CONFIG_SYS_FLASH_QUIET_TEST
144#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
145
146#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
147#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
148#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
149#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
150
151#define CONFIG_SYS_FLASH_EMPTY_INFO
152#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
153#endif
154
155#define CONFIG_NAND_FSL_IFC
156#define CONFIG_SYS_NAND_MAX_ECCPOS 256
157#define CONFIG_SYS_NAND_MAX_OOBFREE 2
158#define CONFIG_SYS_NAND_BASE 0x520000000
159#define CONFIG_SYS_NAND_BASE_PHYS 0x20000000
160
161#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
162#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
163 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
164 | CSPR_MSEL_NAND /* MSEL = NAND */ \
165 | CSPR_V)
166#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
167
168#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
169 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
170 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
171 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
172 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
173 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
174 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
175
176#define CONFIG_SYS_NAND_ONFI_DETECTION
177
178/* ONFI NAND Flash mode0 Timing Params */
179#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
180 FTIM0_NAND_TWP(0x18) | \
181 FTIM0_NAND_TWCHT(0x07) | \
182 FTIM0_NAND_TWH(0x0a))
183#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
184 FTIM1_NAND_TWBE(0x39) | \
185 FTIM1_NAND_TRR(0x0e) | \
186 FTIM1_NAND_TRP(0x18))
187#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
188 FTIM2_NAND_TREH(0x0a) | \
189 FTIM2_NAND_TWHRE(0x1e))
190#define CONFIG_SYS_NAND_FTIM3 0x0
191
192#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
193#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530194#define CONFIG_CMD_NAND
195
196#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
197
York Sunf749db32014-06-23 15:15:56 -0700198#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
199#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
200#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
201#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
202#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
203#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
204#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
205#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
206#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
207
208/* MC firmware */
209#define CONFIG_FSL_MC_ENET
210#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
211#define CONFIG_SYS_LS_MC_FW_IN_NOR
212#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
York Sunf749db32014-06-23 15:15:56 -0700213#define CONFIG_SYS_LS_MC_DPL_IN_NOR
214#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
215/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
J. German Rivera7b3bd9a2015-01-06 13:19:02 -0800216#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024)
York Sunf749db32014-06-23 15:15:56 -0700217#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000
218
219/* Carve the MC private DRAM block from the end of DRAM */
220#ifdef CONFIG_FSL_MC_ENET
221#define CONFIG_SYS_MEM_TOP_HIDE mc_get_dram_block_size()
222#endif
223
224/* Command line configuration */
225#define CONFIG_CMD_CACHE
226#define CONFIG_CMD_BDI
227#define CONFIG_CMD_DHCP
228#define CONFIG_CMD_ENV
229#define CONFIG_CMD_FLASH
230#define CONFIG_CMD_IMI
231#define CONFIG_CMD_MEMORY
232#define CONFIG_CMD_MII
233#define CONFIG_CMD_NET
234#define CONFIG_CMD_PING
235#define CONFIG_CMD_SAVEENV
236#define CONFIG_CMD_RUN
237#define CONFIG_CMD_BOOTD
238#define CONFIG_CMD_ECHO
239#define CONFIG_CMD_SOURCE
240#define CONFIG_CMD_FAT
241#define CONFIG_DOS_PARTITION
242
243/* Miscellaneous configurable options */
244#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
York Sun8bfa3012014-09-08 12:20:01 -0700245#define CONFIG_ARCH_EARLY_INIT_R
York Sunf749db32014-06-23 15:15:56 -0700246
247/* Physical Memory Map */
248/* fixme: these need to be checked against the board */
249#define CONFIG_CHIP_SELECTS_PER_CTRL 4
York Sun064d0312015-01-06 13:18:54 -0800250#define CONFIG_SYS_CLK_FREQ 100000000
251#define CONFIG_DDR_CLK_FREQ 133333333
York Sunf749db32014-06-23 15:15:56 -0700252
253
York Sund9c68b12014-08-13 10:21:05 -0700254#define CONFIG_NR_DRAM_BANKS 3
York Sunf749db32014-06-23 15:15:56 -0700255
York Sunf749db32014-06-23 15:15:56 -0700256#define CONFIG_HWCONFIG
257#define HWCONFIG_BUFFER_SIZE 128
258
259#define CONFIG_DISPLAY_CPUINFO
260
261/* Initial environment variables */
262#define CONFIG_EXTRA_ENV_SETTINGS \
263 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
264 "loadaddr=0x80100000\0" \
265 "kernel_addr=0x100000\0" \
266 "ramdisk_addr=0x800000\0" \
267 "ramdisk_size=0x2000000\0" \
268 "fdt_high=0xffffffffffffffff\0" \
269 "initrd_high=0xffffffffffffffff\0" \
270 "kernel_start=0x581200000\0" \
Stuart Yoder052ddd52015-01-06 13:18:57 -0800271 "kernel_load=0xa0000000\0" \
York Sunf749db32014-06-23 15:15:56 -0700272 "kernel_size=0x1000000\0" \
273 "console=ttyAMA0,38400n8\0"
274
Arnab Basu40e61f82015-01-06 13:18:56 -0800275#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
276 "earlycon=uart8250,mmio,0x21c0600,115200 " \
277 "default_hugepagesz=2m hugepagesz=2m " \
278 "hugepages=16"
York Sunf749db32014-06-23 15:15:56 -0700279#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
280 "$kernel_size && bootm $kernel_load"
281#define CONFIG_BOOTDELAY 1
282
283/* Store environment at top of flash */
284#define CONFIG_ENV_IS_NOWHERE 1
285#define CONFIG_ENV_SIZE 0x1000
286
287/* Monitor Command Prompt */
288#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
289#define CONFIG_SYS_PROMPT "> "
290#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
291 sizeof(CONFIG_SYS_PROMPT) + 16)
292#define CONFIG_SYS_HUSH_PARSER
293#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
294#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
295#define CONFIG_SYS_LONGHELP
296#define CONFIG_CMDLINE_EDITING 1
297#define CONFIG_SYS_MAXARGS 64 /* max command args */
298
299#ifndef __ASSEMBLY__
300unsigned long mc_get_dram_block_size(void);
301#endif
302
303#endif /* __LS2_COMMON_H */