blob: 440085720aab20ed2ed0799b7e42f1ad8c291320 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michael Kurzd4363ba2017-01-22 16:04:30 +01002/*
3 * (C) Copyright 2016
4 *
5 * Michael Kurz, <michi.kurz@gmail.com>
6 *
7 * STM32 QSPI driver
Michael Kurzd4363ba2017-01-22 16:04:30 +01008 */
9
10#include <common.h>
Patrice Chotard8c4592d2018-05-14 15:42:51 +020011#include <clk.h>
Simon Glass340fd102020-07-19 10:15:34 -060012#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060013#include <log.h>
Patrice Chotard5e461232018-05-14 15:42:56 +020014#include <reset.h>
Simon Glass340fd102020-07-19 10:15:34 -060015#include <spi.h>
Christophe Kerello321d1532019-04-05 11:46:50 +020016#include <spi-mem.h>
Simon Glass336d4612020-02-03 07:36:16 -070017#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060018#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060019#include <linux/delay.h>
Christophe Kerello321d1532019-04-05 11:46:50 +020020#include <linux/iopoll.h>
Patrice Chotard2a6ca732018-05-14 15:42:55 +020021#include <linux/ioport.h>
Christophe Kerello321d1532019-04-05 11:46:50 +020022#include <linux/sizes.h>
Michael Kurzd4363ba2017-01-22 16:04:30 +010023
24struct stm32_qspi_regs {
25 u32 cr; /* 0x00 */
26 u32 dcr; /* 0x04 */
27 u32 sr; /* 0x08 */
28 u32 fcr; /* 0x0C */
29 u32 dlr; /* 0x10 */
30 u32 ccr; /* 0x14 */
31 u32 ar; /* 0x18 */
32 u32 abr; /* 0x1C */
33 u32 dr; /* 0x20 */
34 u32 psmkr; /* 0x24 */
35 u32 psmar; /* 0x28 */
36 u32 pir; /* 0x2C */
37 u32 lptr; /* 0x30 */
38};
39
40/*
41 * QUADSPI control register
42 */
43#define STM32_QSPI_CR_EN BIT(0)
44#define STM32_QSPI_CR_ABORT BIT(1)
45#define STM32_QSPI_CR_DMAEN BIT(2)
46#define STM32_QSPI_CR_TCEN BIT(3)
47#define STM32_QSPI_CR_SSHIFT BIT(4)
48#define STM32_QSPI_CR_DFM BIT(6)
49#define STM32_QSPI_CR_FSEL BIT(7)
Christophe Kerello321d1532019-04-05 11:46:50 +020050#define STM32_QSPI_CR_FTHRES_SHIFT 8
Michael Kurzd4363ba2017-01-22 16:04:30 +010051#define STM32_QSPI_CR_TEIE BIT(16)
52#define STM32_QSPI_CR_TCIE BIT(17)
53#define STM32_QSPI_CR_FTIE BIT(18)
54#define STM32_QSPI_CR_SMIE BIT(19)
55#define STM32_QSPI_CR_TOIE BIT(20)
56#define STM32_QSPI_CR_APMS BIT(22)
57#define STM32_QSPI_CR_PMM BIT(23)
58#define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
Christophe Kerello321d1532019-04-05 11:46:50 +020059#define STM32_QSPI_CR_PRESCALER_SHIFT 24
Michael Kurzd4363ba2017-01-22 16:04:30 +010060
61/*
62 * QUADSPI device configuration register
63 */
64#define STM32_QSPI_DCR_CKMODE BIT(0)
65#define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
Christophe Kerello321d1532019-04-05 11:46:50 +020066#define STM32_QSPI_DCR_CSHT_SHIFT 8
Michael Kurzd4363ba2017-01-22 16:04:30 +010067#define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
Christophe Kerello321d1532019-04-05 11:46:50 +020068#define STM32_QSPI_DCR_FSIZE_SHIFT 16
Michael Kurzd4363ba2017-01-22 16:04:30 +010069
70/*
71 * QUADSPI status register
72 */
73#define STM32_QSPI_SR_TEF BIT(0)
74#define STM32_QSPI_SR_TCF BIT(1)
75#define STM32_QSPI_SR_FTF BIT(2)
76#define STM32_QSPI_SR_SMF BIT(3)
77#define STM32_QSPI_SR_TOF BIT(4)
78#define STM32_QSPI_SR_BUSY BIT(5)
Michael Kurzd4363ba2017-01-22 16:04:30 +010079
80/*
81 * QUADSPI flag clear register
82 */
83#define STM32_QSPI_FCR_CTEF BIT(0)
84#define STM32_QSPI_FCR_CTCF BIT(1)
85#define STM32_QSPI_FCR_CSMF BIT(3)
86#define STM32_QSPI_FCR_CTOF BIT(4)
87
88/*
89 * QUADSPI communication configuration register
90 */
91#define STM32_QSPI_CCR_DDRM BIT(31)
92#define STM32_QSPI_CCR_DHHC BIT(30)
93#define STM32_QSPI_CCR_SIOO BIT(28)
Christophe Kerello321d1532019-04-05 11:46:50 +020094#define STM32_QSPI_CCR_FMODE_SHIFT 26
95#define STM32_QSPI_CCR_DMODE_SHIFT 24
96#define STM32_QSPI_CCR_DCYC_SHIFT 18
97#define STM32_QSPI_CCR_ABSIZE_SHIFT 16
98#define STM32_QSPI_CCR_ABMODE_SHIFT 14
99#define STM32_QSPI_CCR_ADSIZE_SHIFT 12
100#define STM32_QSPI_CCR_ADMODE_SHIFT 10
101#define STM32_QSPI_CCR_IMODE_SHIFT 8
Michael Kurzd4363ba2017-01-22 16:04:30 +0100102
Christophe Kerello321d1532019-04-05 11:46:50 +0200103#define STM32_QSPI_CCR_IND_WRITE 0
104#define STM32_QSPI_CCR_IND_READ 1
105#define STM32_QSPI_CCR_MEM_MAP 3
Michael Kurzd4363ba2017-01-22 16:04:30 +0100106
Christophe Kerello321d1532019-04-05 11:46:50 +0200107#define STM32_QSPI_MAX_MMAP_SZ SZ_256M
108#define STM32_QSPI_MAX_CHIP 2
Michael Kurzd4363ba2017-01-22 16:04:30 +0100109
Christophe Kerello321d1532019-04-05 11:46:50 +0200110#define STM32_QSPI_FIFO_TIMEOUT_US 30000
111#define STM32_QSPI_CMD_TIMEOUT_US 1000000
112#define STM32_BUSY_TIMEOUT_US 100000
113#define STM32_ABT_TIMEOUT_US 100000
Michael Kurzd4363ba2017-01-22 16:04:30 +0100114
Christophe Kerello321d1532019-04-05 11:46:50 +0200115struct stm32_qspi_flash {
116 u32 cr;
117 u32 dcr;
118 bool initialized;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100119};
120
121struct stm32_qspi_priv {
122 struct stm32_qspi_regs *regs;
Christophe Kerello321d1532019-04-05 11:46:50 +0200123 struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
124 void __iomem *mm_base;
125 resource_size_t mm_size;
Patrice Chotard541cd6e2017-07-18 09:29:09 +0200126 ulong clock_rate;
Christophe Kerello321d1532019-04-05 11:46:50 +0200127 int cs_used;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100128};
129
Christophe Kerello321d1532019-04-05 11:46:50 +0200130static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
Michael Kurzd4363ba2017-01-22 16:04:30 +0100131{
Christophe Kerello321d1532019-04-05 11:46:50 +0200132 u32 sr;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100133 int ret;
134
Christophe Kerello321d1532019-04-05 11:46:50 +0200135 ret = readl_poll_timeout(&priv->regs->sr, sr,
136 !(sr & STM32_QSPI_SR_BUSY),
137 STM32_BUSY_TIMEOUT_US);
138 if (ret)
139 pr_err("busy timeout (stat:%#x)\n", sr);
140
141 return ret;
142}
143
144static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
145 const struct spi_mem_op *op)
146{
147 u32 sr;
148 int ret;
149
150 if (!op->data.nbytes)
151 return _stm32_qspi_wait_for_not_busy(priv);
152
153 ret = readl_poll_timeout(&priv->regs->sr, sr,
154 sr & STM32_QSPI_SR_TCF,
155 STM32_QSPI_CMD_TIMEOUT_US);
Michael Kurzd4363ba2017-01-22 16:04:30 +0100156 if (ret) {
Christophe Kerello321d1532019-04-05 11:46:50 +0200157 pr_err("cmd timeout (stat:%#x)\n", sr);
158 } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
159 pr_err("transfer error (stat:%#x)\n", sr);
160 ret = -EIO;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100161 }
162
Christophe Kerello321d1532019-04-05 11:46:50 +0200163 /* clear flags */
164 writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
Michael Kurzd4363ba2017-01-22 16:04:30 +0100165
Christophe Kerello321d1532019-04-05 11:46:50 +0200166 return ret;
167}
Michael Kurzd4363ba2017-01-22 16:04:30 +0100168
Christophe Kerello321d1532019-04-05 11:46:50 +0200169static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
170{
171 *val = readb(addr);
172}
173
174static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
175{
176 writeb(*val, addr);
177}
178
179static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
180 const struct spi_mem_op *op)
181{
182 void (*fifo)(u8 *val, void __iomem *addr);
183 u32 len = op->data.nbytes, sr;
184 u8 *buf;
185 int ret;
186
187 if (op->data.dir == SPI_MEM_DATA_IN) {
188 fifo = _stm32_qspi_read_fifo;
189 buf = op->data.buf.in;
190
191 } else {
192 fifo = _stm32_qspi_write_fifo;
193 buf = (u8 *)op->data.buf.out;
194 }
195
196 while (len--) {
197 ret = readl_poll_timeout(&priv->regs->sr, sr,
198 sr & STM32_QSPI_SR_FTF,
199 STM32_QSPI_FIFO_TIMEOUT_US);
200 if (ret) {
201 pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
202 return ret;
203 }
204
205 fifo(buf++, &priv->regs->dr);
206 }
Michael Kurzd4363ba2017-01-22 16:04:30 +0100207
208 return 0;
209}
210
Christophe Kerello321d1532019-04-05 11:46:50 +0200211static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
212 const struct spi_mem_op *op)
213{
214 memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
215 op->data.nbytes);
216
217 return 0;
218}
219
220static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
221 const struct spi_mem_op *op,
222 u8 mode)
223{
224 if (!op->data.nbytes)
225 return 0;
226
227 if (mode == STM32_QSPI_CCR_MEM_MAP)
228 return stm32_qspi_mm(priv, op);
229
230 return _stm32_qspi_poll(priv, op);
231}
232
233static int _stm32_qspi_get_mode(u8 buswidth)
234{
235 if (buswidth == 4)
236 return 3;
237
238 return buswidth;
239}
240
241static int stm32_qspi_exec_op(struct spi_slave *slave,
242 const struct spi_mem_op *op)
243{
244 struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
245 u32 cr, ccr, addr_max;
246 u8 mode = STM32_QSPI_CCR_IND_WRITE;
247 int timeout, ret;
248
249 debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
250 __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
251 op->dummy.buswidth, op->data.buswidth,
252 op->addr.val, op->data.nbytes);
253
254 ret = _stm32_qspi_wait_for_not_busy(priv);
255 if (ret)
256 return ret;
257
258 addr_max = op->addr.val + op->data.nbytes + 1;
259
260 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
261 if (addr_max < priv->mm_size && op->addr.buswidth)
262 mode = STM32_QSPI_CCR_MEM_MAP;
263 else
264 mode = STM32_QSPI_CCR_IND_READ;
265 }
266
267 if (op->data.nbytes)
268 writel(op->data.nbytes - 1, &priv->regs->dlr);
269
270 ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
271 ccr |= op->cmd.opcode;
272 ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
273 << STM32_QSPI_CCR_IMODE_SHIFT);
274
275 if (op->addr.nbytes) {
276 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
277 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
278 << STM32_QSPI_CCR_ADMODE_SHIFT);
279 }
280
281 if (op->dummy.buswidth && op->dummy.nbytes)
282 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
283 << STM32_QSPI_CCR_DCYC_SHIFT);
284
285 if (op->data.nbytes)
286 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
287 << STM32_QSPI_CCR_DMODE_SHIFT);
288
289 writel(ccr, &priv->regs->ccr);
290
291 if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
292 writel(op->addr.val, &priv->regs->ar);
293
294 ret = _stm32_qspi_tx(priv, op, mode);
295 /*
296 * Abort in:
297 * -error case
298 * -read memory map: prefetching must be stopped if we read the last
299 * byte of device (device size - fifo size). like device size is not
300 * knows, the prefetching is always stop.
301 */
302 if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
303 goto abort;
304
305 /* Wait end of tx in indirect mode */
306 ret = _stm32_qspi_wait_cmd(priv, op);
307 if (ret)
308 goto abort;
309
310 return 0;
311
312abort:
313 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
314
315 /* Wait clear of abort bit by hw */
316 timeout = readl_poll_timeout(&priv->regs->cr, cr,
317 !(cr & STM32_QSPI_CR_ABORT),
318 STM32_ABT_TIMEOUT_US);
319
320 writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
321
322 if (ret || timeout)
323 pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
324
325 return ret;
326}
327
Michael Kurzd4363ba2017-01-22 16:04:30 +0100328static int stm32_qspi_probe(struct udevice *bus)
329{
Michael Kurzd4363ba2017-01-22 16:04:30 +0100330 struct stm32_qspi_priv *priv = dev_get_priv(bus);
Christophe Kerello321d1532019-04-05 11:46:50 +0200331 struct resource res;
Patrice Chotard12e7c912018-05-14 15:42:49 +0200332 struct clk clk;
Patrice Chotard5e461232018-05-14 15:42:56 +0200333 struct reset_ctl reset_ctl;
Patrice Chotard12e7c912018-05-14 15:42:49 +0200334 int ret;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100335
Christophe Kerello321d1532019-04-05 11:46:50 +0200336 ret = dev_read_resource_byname(bus, "qspi", &res);
337 if (ret) {
338 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
339 return ret;
340 }
Michael Kurzd4363ba2017-01-22 16:04:30 +0100341
Christophe Kerello321d1532019-04-05 11:46:50 +0200342 priv->regs = (struct stm32_qspi_regs *)res.start;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100343
Christophe Kerello321d1532019-04-05 11:46:50 +0200344 ret = dev_read_resource_byname(bus, "qspi_mm", &res);
345 if (ret) {
346 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
347 return ret;
348 }
Michael Kurzd4363ba2017-01-22 16:04:30 +0100349
Christophe Kerello321d1532019-04-05 11:46:50 +0200350 priv->mm_base = (void __iomem *)res.start;
351
352 priv->mm_size = resource_size(&res);
353 if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
354 return -EINVAL;
355
356 debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
357 __func__, priv->regs, priv->mm_base, priv->mm_size);
Michael Kurzd4363ba2017-01-22 16:04:30 +0100358
Vikas Manocha890bafd2017-04-10 15:02:50 -0700359 ret = clk_get_by_index(bus, 0, &clk);
360 if (ret < 0)
361 return ret;
362
363 ret = clk_enable(&clk);
Vikas Manocha890bafd2017-04-10 15:02:50 -0700364 if (ret) {
365 dev_err(bus, "failed to enable clock\n");
366 return ret;
367 }
Patrice Chotard541cd6e2017-07-18 09:29:09 +0200368
369 priv->clock_rate = clk_get_rate(&clk);
Patrick Delaunay1ddf5442019-06-21 15:26:55 +0200370 if (!priv->clock_rate) {
Patrice Chotard541cd6e2017-07-18 09:29:09 +0200371 clk_disable(&clk);
Patrick Delaunay1ddf5442019-06-21 15:26:55 +0200372 return -EINVAL;
Patrice Chotard541cd6e2017-07-18 09:29:09 +0200373 }
374
Patrice Chotard5e461232018-05-14 15:42:56 +0200375 ret = reset_get_by_index(bus, 0, &reset_ctl);
376 if (ret) {
377 if (ret != -ENOENT) {
378 dev_err(bus, "failed to get reset\n");
379 clk_disable(&clk);
380 return ret;
381 }
382 } else {
383 /* Reset QSPI controller */
384 reset_assert(&reset_ctl);
385 udelay(2);
386 reset_deassert(&reset_ctl);
387 }
Michael Kurzd4363ba2017-01-22 16:04:30 +0100388
Christophe Kerello321d1532019-04-05 11:46:50 +0200389 priv->cs_used = -1;
390
Michael Kurzd4363ba2017-01-22 16:04:30 +0100391 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
392
Christophe Kerello321d1532019-04-05 11:46:50 +0200393 /* Set dcr fsize to max address */
394 setbits_le32(&priv->regs->dcr,
395 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
Michael Kurzd4363ba2017-01-22 16:04:30 +0100396
Michael Kurzd4363ba2017-01-22 16:04:30 +0100397 return 0;
398}
399
400static int stm32_qspi_claim_bus(struct udevice *dev)
401{
Christophe Kerello321d1532019-04-05 11:46:50 +0200402 struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
Simon Glass8a8d24b2020-12-03 16:55:23 -0700403 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
Patrick Delaunay1ddf5442019-06-21 15:26:55 +0200404 int slave_cs = slave_plat->cs;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100405
Patrick Delaunay1ddf5442019-06-21 15:26:55 +0200406 if (slave_cs >= STM32_QSPI_MAX_CHIP)
Christophe Kerello495f3b22018-05-14 15:42:54 +0200407 return -ENODEV;
408
Patrick Delaunay1ddf5442019-06-21 15:26:55 +0200409 if (priv->cs_used != slave_cs) {
410 struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
Michael Kurzd4363ba2017-01-22 16:04:30 +0100411
Patrick Delaunay1ddf5442019-06-21 15:26:55 +0200412 priv->cs_used = slave_cs;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100413
Christophe Kerello321d1532019-04-05 11:46:50 +0200414 if (flash->initialized) {
415 /* Set the configuration: speed + cs */
416 writel(flash->cr, &priv->regs->cr);
417 writel(flash->dcr, &priv->regs->dcr);
418 } else {
419 /* Set chip select */
420 clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
421 priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
422
423 /* Save the configuration: speed + cs */
424 flash->cr = readl(&priv->regs->cr);
425 flash->dcr = readl(&priv->regs->dcr);
426
427 flash->initialized = true;
428 }
429 }
430
431 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
Michael Kurzd4363ba2017-01-22 16:04:30 +0100432
433 return 0;
434}
435
436static int stm32_qspi_release_bus(struct udevice *dev)
437{
Christophe Kerello321d1532019-04-05 11:46:50 +0200438 struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
Michael Kurzd4363ba2017-01-22 16:04:30 +0100439
Christophe Kerello321d1532019-04-05 11:46:50 +0200440 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
Michael Kurzd4363ba2017-01-22 16:04:30 +0100441
442 return 0;
443}
444
Michael Kurzd4363ba2017-01-22 16:04:30 +0100445static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
446{
Michael Kurzd4363ba2017-01-22 16:04:30 +0100447 struct stm32_qspi_priv *priv = dev_get_priv(bus);
Patrick Delaunay936abad2018-05-14 15:42:50 +0200448 u32 qspi_clk = priv->clock_rate;
449 u32 prescaler = 255;
450 u32 csht;
Christophe Kerello321d1532019-04-05 11:46:50 +0200451 int ret;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100452
Michael Kurzd4363ba2017-01-22 16:04:30 +0100453 if (speed > 0) {
Patrick Delaunay1ddf5442019-06-21 15:26:55 +0200454 prescaler = 0;
455 if (qspi_clk) {
456 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
457 if (prescaler > 255)
458 prescaler = 255;
459 }
Michael Kurzd4363ba2017-01-22 16:04:30 +0100460 }
461
Patrick Delaunay936abad2018-05-14 15:42:50 +0200462 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
Michael Kurzd4363ba2017-01-22 16:04:30 +0100463 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
464
Christophe Kerello321d1532019-04-05 11:46:50 +0200465 ret = _stm32_qspi_wait_for_not_busy(priv);
466 if (ret)
467 return ret;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100468
469 clrsetbits_le32(&priv->regs->cr,
470 STM32_QSPI_CR_PRESCALER_MASK <<
471 STM32_QSPI_CR_PRESCALER_SHIFT,
472 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
473
Michael Kurzd4363ba2017-01-22 16:04:30 +0100474 clrsetbits_le32(&priv->regs->dcr,
475 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
476 csht << STM32_QSPI_DCR_CSHT_SHIFT);
477
478 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
479 (qspi_clk / (prescaler + 1)));
480
481 return 0;
482}
483
484static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
485{
486 struct stm32_qspi_priv *priv = dev_get_priv(bus);
Christophe Kerello321d1532019-04-05 11:46:50 +0200487 int ret;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100488
Christophe Kerello321d1532019-04-05 11:46:50 +0200489 ret = _stm32_qspi_wait_for_not_busy(priv);
490 if (ret)
491 return ret;
Michael Kurzd4363ba2017-01-22 16:04:30 +0100492
493 if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
494 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
495 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
496 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
497 else
498 return -ENODEV;
499
500 if (mode & SPI_CS_HIGH)
501 return -ENODEV;
502
Michael Kurzd4363ba2017-01-22 16:04:30 +0100503 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
504
505 if (mode & SPI_RX_QUAD)
506 debug("quad, tx: ");
507 else if (mode & SPI_RX_DUAL)
508 debug("dual, tx: ");
509 else
510 debug("single, tx: ");
511
512 if (mode & SPI_TX_QUAD)
513 debug("quad\n");
514 else if (mode & SPI_TX_DUAL)
515 debug("dual\n");
516 else
517 debug("single\n");
518
519 return 0;
520}
521
Christophe Kerello321d1532019-04-05 11:46:50 +0200522static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
523 .exec_op = stm32_qspi_exec_op,
524};
525
Michael Kurzd4363ba2017-01-22 16:04:30 +0100526static const struct dm_spi_ops stm32_qspi_ops = {
527 .claim_bus = stm32_qspi_claim_bus,
528 .release_bus = stm32_qspi_release_bus,
Michael Kurzd4363ba2017-01-22 16:04:30 +0100529 .set_speed = stm32_qspi_set_speed,
530 .set_mode = stm32_qspi_set_mode,
Christophe Kerello321d1532019-04-05 11:46:50 +0200531 .mem_ops = &stm32_qspi_mem_ops,
Michael Kurzd4363ba2017-01-22 16:04:30 +0100532};
533
534static const struct udevice_id stm32_qspi_ids[] = {
Christophe Kerello76afe562018-05-14 15:42:53 +0200535 { .compatible = "st,stm32f469-qspi" },
Michael Kurzd4363ba2017-01-22 16:04:30 +0100536 { }
537};
538
539U_BOOT_DRIVER(stm32_qspi) = {
Christophe Kerello321d1532019-04-05 11:46:50 +0200540 .name = "stm32_qspi",
541 .id = UCLASS_SPI,
Michael Kurzd4363ba2017-01-22 16:04:30 +0100542 .of_match = stm32_qspi_ids,
Christophe Kerello321d1532019-04-05 11:46:50 +0200543 .ops = &stm32_qspi_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700544 .priv_auto = sizeof(struct stm32_qspi_priv),
Christophe Kerello321d1532019-04-05 11:46:50 +0200545 .probe = stm32_qspi_probe,
Michael Kurzd4363ba2017-01-22 16:04:30 +0100546};