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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ashish Kumare84a3242017-08-31 16:12:54 +05302/*
3 * Copyright 2017 NXP
Ashish Kumare84a3242017-08-31 16:12:54 +05304 */
5
6#ifndef __LS1088A_DDR_H__
7#define __LS1088A_DDR_H__
8struct board_specific_parameters {
9 u32 n_ranks;
10 u32 datarate_mhz_high;
11 u32 rank_gb;
12 u32 clk_adjust;
13 u32 wrlvl_start;
14 u32 wrlvl_ctl_2;
15 u32 wrlvl_ctl_3;
16};
17
18/*
19 * These tables contain all valid speeds we want to override with board
20 * specific parameters. datarate_mhz_high values need to be in ascending order
21 * for each n_ranks group.
22 */
23
24static const struct board_specific_parameters udimm0[] = {
25 /*
26 * memory controller 0
27 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
29 */
30#if defined(CONFIG_TARGET_LS1088ARDB)
31
32 {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},
Ashish Kumar7d3a5322018-04-18 10:37:24 +053033 {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,},
Ashish Kumare84a3242017-08-31 16:12:54 +053034 {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
35 {}
Ashish Kumar77697762017-08-31 16:12:55 +053036#elif defined(CONFIG_TARGET_LS1088AQDS)
37 {2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,},
Ashish Kumar7d3a5322018-04-18 10:37:24 +053038 {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,},
Ashish Kumar77697762017-08-31 16:12:55 +053039 {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,},
40 {}
Ashish Kumare84a3242017-08-31 16:12:54 +053041
42#endif
43};
44
45static const struct board_specific_parameters *udimms[] = {
46 udimm0,
47};
48#endif