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Sergei Poselenov5d108ac2008-04-30 11:42:50 +02001/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <common.h>
26#include <asm/processor.h>
27#include <asm/immap_85xx.h>
Kumar Galabe0bd822008-08-26 22:56:56 -050028#include <asm/fsl_ddr_sdram.h>
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020029#include <asm/processor.h>
30#include <asm/mmu.h>
31#include <spd_sdram.h>
32
33
34#if !defined(CONFIG_SPD_EEPROM)
35/*
36 * Autodetect onboard DDR SDRAM on 85xx platforms
37 *
38 * NOTE: Some of the hardcoded values are hardware dependant,
39 * so this should be extended for other future boards
40 * using this routine!
41 */
42long int sdram_setup(int casl)
43{
44 volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
45
46 /*
47 * Disable memory controller.
48 */
49 ddr->cs0_config = 0;
50 ddr->sdram_cfg = 0;
51
52 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
53 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
54 ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
55 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
56 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
57 ddr->sdram_mode = CFG_DDR_MODE;
58 ddr->sdram_interval = CFG_DDR_INTERVAL;
59 ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2;
60 ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL;
61
62 asm ("sync;isync;msync");
63 udelay(1000);
64
65 ddr->sdram_cfg = CFG_DDR_CONFIG;
66 asm ("sync; isync; msync");
67 udelay(1000);
68
69 if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) {
70 /*
71 * OK, size detected -> all done
72 */
73 return CFG_SDRAM_SIZE<<20;
74 }
75
76 return 0; /* nothing found ! */
77}
78#endif
79
Becky Bruce9973e3c2008-06-09 16:03:40 -050080phys_size_t initdram (int board_type)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020081{
82 long dram_size = 0;
83#if defined(CONFIG_SPD_EEPROM)
Kumar Galabe0bd822008-08-26 22:56:56 -050084 dram_size = fsl_ddr_sdram();
85 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
86 dram_size *= 0x100000;
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020087#else
88 dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
89#endif
90 return dram_size;
91}
92
93#if defined(CFG_DRAM_TEST)
94int testdram (void)
95{
96 uint *pstart = (uint *) CFG_MEMTEST_START;
97 uint *pend = (uint *) CFG_MEMTEST_END;
98 uint *p;
99
100 printf ("SDRAM test phase 1:\n");
101 for (p = pstart; p < pend; p++)
102 *p = 0xaaaaaaaa;
103
104 for (p = pstart; p < pend; p++) {
105 if (*p != 0xaaaaaaaa) {
106 printf ("SDRAM test fails at: %08x\n", (uint) p);
107 return 1;
108 }
109 }
110
111 printf ("SDRAM test phase 2:\n");
112 for (p = pstart; p < pend; p++)
113 *p = 0x55555555;
114
115 for (p = pstart; p < pend; p++) {
116 if (*p != 0x55555555) {
117 printf ("SDRAM test fails at: %08x\n", (uint) p);
118 return 1;
119 }
120 }
121
122 printf ("SDRAM test passed.\n");
123 return 0;
124}
125#endif