blob: 160178207d3a35e5c982785029145621897d32bb [file] [log] [blame]
wdenkea8015b2002-10-26 16:43:06 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29
30#define FLASH_BANK_SIZE 0x400000
31#define MAIN_SECT_SIZE 0x20000
32
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
wdenkea8015b2002-10-26 16:43:06 +000034
35
36/*-----------------------------------------------------------------------
37 */
38
wdenk63cfcbb2004-10-09 22:32:26 +000039ulong flash_init (void)
wdenkea8015b2002-10-26 16:43:06 +000040{
wdenk63cfcbb2004-10-09 22:32:26 +000041 int i, j;
42 ulong size = 0;
wdenkea8015b2002-10-26 16:43:06 +000043
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
wdenk63cfcbb2004-10-09 22:32:26 +000045 ulong flashbase = 0;
wdenkea8015b2002-10-26 16:43:06 +000046
wdenk63cfcbb2004-10-09 22:32:26 +000047 flash_info[i].flash_id =
48 (INTEL_MANUFACT & FLASH_VENDMASK) |
49 (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
50 flash_info[i].size = FLASH_BANK_SIZE;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051 flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
52 memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
wdenk63cfcbb2004-10-09 22:32:26 +000053 switch (i) {
54 case 0:
55 flashbase = PHYS_FLASH_1;
56 break;
57 case 1:
58 flashbase = PHYS_FLASH_2;
59 break;
60 default:
61 panic ("configured too many flash banks!\n");
62 break;
63 }
64 for (j = 0; j < flash_info[i].sector_count; j++) {
65 flash_info[i].start[j] =
66 flashbase + j * MAIN_SECT_SIZE;
67 }
68 size += flash_info[i].size;
69 }
wdenkea8015b2002-10-26 16:43:06 +000070
wdenk63cfcbb2004-10-09 22:32:26 +000071 /* Protect monitor and environment sectors
72 */
73 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074 CONFIG_SYS_FLASH_BASE,
75 CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
wdenk63cfcbb2004-10-09 22:32:26 +000076 &flash_info[0]);
wdenkea8015b2002-10-26 16:43:06 +000077
wdenk63cfcbb2004-10-09 22:32:26 +000078 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020079 CONFIG_ENV_ADDR,
80 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
wdenk63cfcbb2004-10-09 22:32:26 +000081
82 return size;
wdenkea8015b2002-10-26 16:43:06 +000083}
84
85/*-----------------------------------------------------------------------
86 */
wdenk63cfcbb2004-10-09 22:32:26 +000087void flash_print_info (flash_info_t * info)
wdenkea8015b2002-10-26 16:43:06 +000088{
wdenk63cfcbb2004-10-09 22:32:26 +000089 int i, j;
wdenkea8015b2002-10-26 16:43:06 +000090
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
wdenk63cfcbb2004-10-09 22:32:26 +000092 switch (info->flash_id & FLASH_VENDMASK) {
93 case (INTEL_MANUFACT & FLASH_VENDMASK):
94 printf ("Intel: ");
95 break;
96 default:
97 printf ("Unknown Vendor ");
98 break;
99 }
wdenkea8015b2002-10-26 16:43:06 +0000100
wdenk63cfcbb2004-10-09 22:32:26 +0000101 switch (info->flash_id & FLASH_TYPEMASK) {
102 case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
103 printf ("28F320J3A (32Mbit)\n");
104 break;
105 case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
106 printf ("28F128J3 (128Mbit)\n");
107 break;
108 default:
109 printf ("Unknown Chip Type\n");
110 goto Done;
111 break;
112 }
wdenkea8015b2002-10-26 16:43:06 +0000113
wdenk63cfcbb2004-10-09 22:32:26 +0000114 printf (" Size: %ld MB in %d Sectors\n",
115 info->size >> 20, info->sector_count);
wdenkea8015b2002-10-26 16:43:06 +0000116
wdenk63cfcbb2004-10-09 22:32:26 +0000117 printf (" Sector Start Addresses:");
118 for (i = 0; i < info->sector_count; i++) {
119 if ((i % 5) == 0) {
120 printf ("\n ");
121 }
122 printf (" %08lX%s", info->start[i],
123 info->protect[i] ? " (RO)" : " ");
124 }
125 printf ("\n");
126 info++;
127 }
wdenkea8015b2002-10-26 16:43:06 +0000128
wdenk63cfcbb2004-10-09 22:32:26 +0000129Done: ;
wdenkea8015b2002-10-26 16:43:06 +0000130}
131
132/*-----------------------------------------------------------------------
133 */
134
wdenk63cfcbb2004-10-09 22:32:26 +0000135int flash_erase (flash_info_t * info, int s_first, int s_last)
wdenkea8015b2002-10-26 16:43:06 +0000136{
wdenk63cfcbb2004-10-09 22:32:26 +0000137 int flag, prot, sect;
138 int rc = ERR_OK;
Graeme Russa60d1e52011-07-15 23:31:37 +0000139 ulong start;
wdenkea8015b2002-10-26 16:43:06 +0000140
wdenk63cfcbb2004-10-09 22:32:26 +0000141 if (info->flash_id == FLASH_UNKNOWN)
142 return ERR_UNKNOWN_FLASH_TYPE;
wdenkea8015b2002-10-26 16:43:06 +0000143
wdenk63cfcbb2004-10-09 22:32:26 +0000144 if ((s_first < 0) || (s_first > s_last)) {
145 return ERR_INVAL;
146 }
wdenkea8015b2002-10-26 16:43:06 +0000147
wdenk63cfcbb2004-10-09 22:32:26 +0000148 if ((info->flash_id & FLASH_VENDMASK) !=
149 (INTEL_MANUFACT & FLASH_VENDMASK)) {
150 return ERR_UNKNOWN_FLASH_VENDOR;
151 }
wdenkea8015b2002-10-26 16:43:06 +0000152
wdenk63cfcbb2004-10-09 22:32:26 +0000153 prot = 0;
154 for (sect = s_first; sect <= s_last; ++sect) {
155 if (info->protect[sect]) {
156 prot++;
157 }
158 }
159 if (prot)
160 return ERR_PROTECTED;
wdenkea8015b2002-10-26 16:43:06 +0000161
wdenk63cfcbb2004-10-09 22:32:26 +0000162 /*
163 * Disable interrupts which might cause a timeout
164 * here. Remember that our exception vectors are
165 * at address 0 in the flash, and we don't want a
166 * (ticker) exception to happen while the flash
167 * chip is in programming mode.
168 */
169 flag = disable_interrupts ();
wdenkea8015b2002-10-26 16:43:06 +0000170
wdenk63cfcbb2004-10-09 22:32:26 +0000171 /* Start erase on unprotected sectors */
172 for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
wdenkea8015b2002-10-26 16:43:06 +0000173
wdenk63cfcbb2004-10-09 22:32:26 +0000174 printf ("Erasing sector %2d ... ", sect);
wdenkea8015b2002-10-26 16:43:06 +0000175
wdenk63cfcbb2004-10-09 22:32:26 +0000176 /* arm simple, non interrupt dependent timer */
Graeme Russa60d1e52011-07-15 23:31:37 +0000177 start = get_timer(0);
wdenkea8015b2002-10-26 16:43:06 +0000178
wdenk63cfcbb2004-10-09 22:32:26 +0000179 if (info->protect[sect] == 0) { /* not protected */
180 vu_short *addr = (vu_short *) (info->start[sect]);
wdenkea8015b2002-10-26 16:43:06 +0000181
wdenk63cfcbb2004-10-09 22:32:26 +0000182 *addr = 0x20; /* erase setup */
183 *addr = 0xD0; /* erase confirm */
wdenkea8015b2002-10-26 16:43:06 +0000184
wdenk63cfcbb2004-10-09 22:32:26 +0000185 while ((*addr & 0x80) != 0x80) {
Graeme Russa60d1e52011-07-15 23:31:37 +0000186 if (get_timer(start) >
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187 CONFIG_SYS_FLASH_ERASE_TOUT) {
wdenk63cfcbb2004-10-09 22:32:26 +0000188 *addr = 0xB0; /* suspend erase */
189 *addr = 0xFF; /* reset to read mode */
190 rc = ERR_TIMOUT;
191 goto outahere;
192 }
193 }
wdenkea8015b2002-10-26 16:43:06 +0000194
wdenk63cfcbb2004-10-09 22:32:26 +0000195 /* clear status register command */
196 *addr = 0x50;
197 /* reset to read mode */
198 *addr = 0xFF;
199 }
200 printf ("ok.\n");
201 }
202 if (ctrlc ())
203 printf ("User Interrupt!\n");
wdenkea8015b2002-10-26 16:43:06 +0000204
205outahere:
206
wdenk63cfcbb2004-10-09 22:32:26 +0000207 /* allow flash to settle - wait 10 ms */
208 udelay_masked (10000);
wdenkea8015b2002-10-26 16:43:06 +0000209
wdenk63cfcbb2004-10-09 22:32:26 +0000210 if (flag)
211 enable_interrupts ();
wdenkea8015b2002-10-26 16:43:06 +0000212
wdenk63cfcbb2004-10-09 22:32:26 +0000213 return rc;
wdenkea8015b2002-10-26 16:43:06 +0000214}
215
216/*-----------------------------------------------------------------------
217 * Copy memory to flash
218 */
219
wdenk63cfcbb2004-10-09 22:32:26 +0000220static int write_word (flash_info_t * info, ulong dest, ushort data)
wdenkea8015b2002-10-26 16:43:06 +0000221{
wdenk63cfcbb2004-10-09 22:32:26 +0000222 vu_short *addr = (vu_short *) dest, val;
223 int rc = ERR_OK;
224 int flag;
Graeme Russa60d1e52011-07-15 23:31:37 +0000225 ulong start;
wdenkea8015b2002-10-26 16:43:06 +0000226
wdenk63cfcbb2004-10-09 22:32:26 +0000227 /* Check if Flash is (sufficiently) erased
228 */
229 if ((*addr & data) != data)
230 return ERR_NOT_ERASED;
wdenkea8015b2002-10-26 16:43:06 +0000231
wdenk63cfcbb2004-10-09 22:32:26 +0000232 /*
233 * Disable interrupts which might cause a timeout
234 * here. Remember that our exception vectors are
235 * at address 0 in the flash, and we don't want a
236 * (ticker) exception to happen while the flash
237 * chip is in programming mode.
238 */
239 flag = disable_interrupts ();
wdenkea8015b2002-10-26 16:43:06 +0000240
wdenk63cfcbb2004-10-09 22:32:26 +0000241 /* clear status register command */
242 *addr = 0x50;
wdenkea8015b2002-10-26 16:43:06 +0000243
wdenk63cfcbb2004-10-09 22:32:26 +0000244 /* program set-up command */
245 *addr = 0x40;
wdenkea8015b2002-10-26 16:43:06 +0000246
wdenk63cfcbb2004-10-09 22:32:26 +0000247 /* latch address/data */
248 *addr = data;
wdenkea8015b2002-10-26 16:43:06 +0000249
wdenk63cfcbb2004-10-09 22:32:26 +0000250 /* arm simple, non interrupt dependent timer */
Graeme Russa60d1e52011-07-15 23:31:37 +0000251 start = get_timer(0);
wdenkea8015b2002-10-26 16:43:06 +0000252
wdenk63cfcbb2004-10-09 22:32:26 +0000253 /* wait while polling the status register */
254 while (((val = *addr) & 0x80) != 0x80) {
Graeme Russa60d1e52011-07-15 23:31:37 +0000255 if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
wdenk63cfcbb2004-10-09 22:32:26 +0000256 rc = ERR_TIMOUT;
257 /* suspend program command */
258 *addr = 0xB0;
259 goto outahere;
260 }
261 }
wdenkea8015b2002-10-26 16:43:06 +0000262
wdenk63cfcbb2004-10-09 22:32:26 +0000263 if (val & 0x1A) { /* check for error */
264 printf ("\nFlash write error %02x at address %08lx\n",
265 (int) val, (unsigned long) dest);
266 if (val & (1 << 3)) {
267 printf ("Voltage range error.\n");
268 rc = ERR_PROG_ERROR;
269 goto outahere;
270 }
271 if (val & (1 << 1)) {
272 printf ("Device protect error.\n");
273 rc = ERR_PROTECTED;
274 goto outahere;
275 }
276 if (val & (1 << 4)) {
277 printf ("Programming error.\n");
278 rc = ERR_PROG_ERROR;
279 goto outahere;
280 }
281 rc = ERR_PROG_ERROR;
282 goto outahere;
283 }
wdenkea8015b2002-10-26 16:43:06 +0000284
285outahere:
wdenk63cfcbb2004-10-09 22:32:26 +0000286 /* read array command */
287 *addr = 0xFF;
wdenkea8015b2002-10-26 16:43:06 +0000288
wdenk63cfcbb2004-10-09 22:32:26 +0000289 if (flag)
290 enable_interrupts ();
wdenkea8015b2002-10-26 16:43:06 +0000291
wdenk63cfcbb2004-10-09 22:32:26 +0000292 return rc;
wdenkea8015b2002-10-26 16:43:06 +0000293}
294
295/*-----------------------------------------------------------------------
296 * Copy memory to flash.
297 */
298
wdenk63cfcbb2004-10-09 22:32:26 +0000299int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
wdenkea8015b2002-10-26 16:43:06 +0000300{
wdenk63cfcbb2004-10-09 22:32:26 +0000301 ulong cp, wp;
302 ushort data;
303 int l;
304 int i, rc;
wdenkea8015b2002-10-26 16:43:06 +0000305
wdenk63cfcbb2004-10-09 22:32:26 +0000306 wp = (addr & ~1); /* get lower word aligned address */
wdenkea8015b2002-10-26 16:43:06 +0000307
wdenk63cfcbb2004-10-09 22:32:26 +0000308 /*
309 * handle unaligned start bytes
310 */
311 if ((l = addr - wp) != 0) {
312 data = 0;
313 for (i = 0, cp = wp; i < l; ++i, ++cp) {
314 data = (data >> 8) | (*(uchar *) cp << 8);
315 }
316 for (; i < 2 && cnt > 0; ++i) {
317 data = (data >> 8) | (*src++ << 8);
318 --cnt;
319 ++cp;
320 }
321 for (; cnt == 0 && i < 2; ++i, ++cp) {
322 data = (data >> 8) | (*(uchar *) cp << 8);
323 }
wdenkea8015b2002-10-26 16:43:06 +0000324
wdenk63cfcbb2004-10-09 22:32:26 +0000325 if ((rc = write_word (info, wp, data)) != 0) {
326 return (rc);
327 }
328 wp += 2;
329 }
wdenkea8015b2002-10-26 16:43:06 +0000330
wdenk63cfcbb2004-10-09 22:32:26 +0000331 /*
332 * handle word aligned part
333 */
334 while (cnt >= 2) {
335 data = *((vu_short *) src);
336 if ((rc = write_word (info, wp, data)) != 0) {
337 return (rc);
338 }
339 src += 2;
340 wp += 2;
341 cnt -= 2;
342 }
wdenkea8015b2002-10-26 16:43:06 +0000343
wdenk63cfcbb2004-10-09 22:32:26 +0000344 if (cnt == 0) {
345 return ERR_OK;
346 }
wdenkea8015b2002-10-26 16:43:06 +0000347
wdenk63cfcbb2004-10-09 22:32:26 +0000348 /*
349 * handle unaligned tail bytes
350 */
351 data = 0;
352 for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
353 data = (data >> 8) | (*src++ << 8);
354 --cnt;
355 }
356 for (; i < 2; ++i, ++cp) {
357 data = (data >> 8) | (*(uchar *) cp << 8);
358 }
wdenkea8015b2002-10-26 16:43:06 +0000359
wdenk63cfcbb2004-10-09 22:32:26 +0000360 return write_word (info, wp, data);
wdenkea8015b2002-10-26 16:43:06 +0000361}