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wdenkbf9e3b32004-02-12 00:47:09 +00001/*
2 * Configuation settings for the Motorola MC5272C3 board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
wdenk4e5ca3e2003-12-08 01:34:36 +000024
wdenkbf9e3b32004-02-12 00:47:09 +000025/*
26 * board/config.h - configuration options, board specific
27 */
wdenk4e5ca3e2003-12-08 01:34:36 +000028
wdenkbf9e3b32004-02-12 00:47:09 +000029#ifndef _M5272C3_H
30#define _M5272C3_H
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050036#define CONFIG_MCF52x2 /* define processor family */
37#define CONFIG_M5272 /* define processor type */
wdenk4e5ca3e2003-12-08 01:34:36 +000038
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050039#define CONFIG_MCFTMR
wdenk4e5ca3e2003-12-08 01:34:36 +000040
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050041#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew79e07992008-08-15 16:50:07 +000043#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
wdenk4e5ca3e2003-12-08 01:34:36 +000045
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050046#undef CONFIG_WATCHDOG
wdenkbf9e3b32004-02-12 00:47:09 +000047#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
48
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050049#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
wdenkbf9e3b32004-02-12 00:47:09 +000050
51/* Configuration for environment
52 * Environment is embedded in u-boot in the second sector of the flash
53 */
54#ifndef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020055#define CONFIG_ENV_OFFSET 0x4000
56#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020057#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbf9e3b32004-02-12 00:47:09 +000058#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020059#define CONFIG_ENV_ADDR 0xffe04000
60#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020061#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbf9e3b32004-02-12 00:47:09 +000062#endif
63
Jon Loeliger8353e132007-07-08 14:14:17 -050064/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050065 * BOOTP options
66 */
67#define CONFIG_BOOTP_BOOTFILESIZE
68#define CONFIG_BOOTP_BOOTPATH
69#define CONFIG_BOOTP_GATEWAY
70#define CONFIG_BOOTP_HOSTNAME
71
Jon Loeliger659e2f62007-07-10 09:10:49 -050072/*
Jon Loeliger8353e132007-07-08 14:14:17 -050073 * Command line configuration.
74 */
75#include <config_cmd_default.h>
76
TsiChung Liewdd9f0542010-03-11 22:12:53 -060077#define CONFIG_CMD_CACHE
Jon Loeliger8353e132007-07-08 14:14:17 -050078#define CONFIG_CMD_MII
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050079#define CONFIG_CMD_NET
80#define CONFIG_CMD_PING
81#define CONFIG_CMD_MISC
82#define CONFIG_CMD_ELF
83#define CONFIG_CMD_FLASH
84#define CONFIG_CMD_MEMORY
Jon Loeliger8353e132007-07-08 14:14:17 -050085
86#undef CONFIG_CMD_LOADS
87#undef CONFIG_CMD_LOADB
88
wdenkbf9e3b32004-02-12 00:47:09 +000089#define CONFIG_BOOTDELAY 5
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050090#define CONFIG_MCFFEC
91#ifdef CONFIG_MCFFEC
92# define CONFIG_NET_MULTI 1
93# define CONFIG_MII 1
TsiChung Liewd53cf6a2008-08-19 00:37:13 +060094# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095# define CONFIG_SYS_DISCOVER_PHY
96# define CONFIG_SYS_RX_ETH_BUFFER 8
97# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099# define CONFIG_SYS_FEC0_PINMUX 0
100# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200101# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
103# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500104# define FECDUPLEX FULL
105# define FECSPEED _100BASET
106# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
108# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500109# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500111#endif
112
113#ifdef CONFIG_MCFFEC
114# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
115# define CONFIG_IPADDR 192.162.1.2
116# define CONFIG_NETMASK 255.255.255.0
117# define CONFIG_SERVERIP 192.162.1.1
118# define CONFIG_GATEWAYIP 192.162.1.1
119# define CONFIG_OVERWRITE_ETHADDR_ONCE
120#endif /* CONFIG_MCFFEC */
121
122#define CONFIG_HOSTNAME M5272C3
123#define CONFIG_EXTRA_ENV_SETTINGS \
124 "netdev=eth0\0" \
125 "loadaddr=10000\0" \
126 "u-boot=u-boot.bin\0" \
127 "load=tftp ${loadaddr) ${u-boot}\0" \
128 "upd=run load; run prog\0" \
129 "prog=prot off ffe00000 ffe3ffff;" \
130 "era ffe00000 ffe3ffff;" \
131 "cp.b ${loadaddr} ffe00000 ${filesize};"\
132 "save\0" \
133 ""
wdenkbf9e3b32004-02-12 00:47:09 +0000134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_PROMPT "-> "
136#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkbf9e3b32004-02-12 00:47:09 +0000137
Jon Loeliger8353e132007-07-08 14:14:17 -0500138#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000140#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000142#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
145#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
146#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
147#define CONFIG_SYS_LOAD_ADDR 0x20000
148#define CONFIG_SYS_MEMTEST_START 0x400
149#define CONFIG_SYS_MEMTEST_END 0x380000
150#define CONFIG_SYS_HZ 1000
151#define CONFIG_SYS_CLK 66000000
wdenkbf9e3b32004-02-12 00:47:09 +0000152
153/*
154 * Low Level Configuration Settings
155 * (address mappings, register initial values, etc.)
156 * You should know what you are doing if you make changes here.
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
159#define CONFIG_SYS_SCR 0x0003
160#define CONFIG_SYS_SPR 0xffff
wdenkbf9e3b32004-02-12 00:47:09 +0000161
wdenkbf9e3b32004-02-12 00:47:09 +0000162/*-----------------------------------------------------------------------
163 * Definitions for initial stack pointer and data area (in DPRAM)
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200166#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200167#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkbf9e3b32004-02-12 00:47:09 +0000169
170/*-----------------------------------------------------------------------
171 * Start addresses for the final memory configuration
172 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkbf9e3b32004-02-12 00:47:09 +0000174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_SDRAM_BASE 0x00000000
176#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
177#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenkbf9e3b32004-02-12 00:47:09 +0000178
179#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenkbf9e3b32004-02-12 00:47:09 +0000181#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenkbf9e3b32004-02-12 00:47:09 +0000183#endif
184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_MONITOR_LEN 0x20000
186#define CONFIG_SYS_MALLOC_LEN (256 << 10)
187#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkbf9e3b32004-02-12 00:47:09 +0000188
189/*
190 * For booting Linux, the board info and command line data
191 * have to be in the first 8 MB of memory, since this is
192 * the maximum mapped by the Linux kernel during initialization ??
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
wdenkbf9e3b32004-02-12 00:47:09 +0000195
TsiChung Liewb2028162008-10-21 14:19:26 +0000196/*
wdenkbf9e3b32004-02-12 00:47:09 +0000197 * FLASH organization
198 */
TsiChung Liewb2028162008-10-21 14:19:26 +0000199#define CONFIG_SYS_FLASH_CFI
200#ifdef CONFIG_SYS_FLASH_CFI
201# define CONFIG_FLASH_CFI_DRIVER 1
202# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
203# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
204# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
205# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
206# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
207#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000208
209/*-----------------------------------------------------------------------
210 * Cache Configuration
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkbf9e3b32004-02-12 00:47:09 +0000213
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600214#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200215 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600216#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200217 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600218#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
219#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
220 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
221 CF_ACR_EN | CF_ACR_SM_ALL)
222#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
223 CF_CACR_DISD | CF_CACR_INVI | \
224 CF_CACR_CEIB | CF_CACR_DCM | \
225 CF_CACR_EUSP)
226
wdenkbf9e3b32004-02-12 00:47:09 +0000227/*-----------------------------------------------------------------------
228 * Memory bank definitions
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
231#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
232#define CONFIG_SYS_BR1_PRELIM 0
233#define CONFIG_SYS_OR1_PRELIM 0
234#define CONFIG_SYS_BR2_PRELIM 0x30000001
235#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
236#define CONFIG_SYS_BR3_PRELIM 0
237#define CONFIG_SYS_OR3_PRELIM 0
238#define CONFIG_SYS_BR4_PRELIM 0
239#define CONFIG_SYS_OR4_PRELIM 0
240#define CONFIG_SYS_BR5_PRELIM 0
241#define CONFIG_SYS_OR5_PRELIM 0
242#define CONFIG_SYS_BR6_PRELIM 0
243#define CONFIG_SYS_OR6_PRELIM 0
244#define CONFIG_SYS_BR7_PRELIM 0x00000701
245#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
wdenkbf9e3b32004-02-12 00:47:09 +0000246
247/*-----------------------------------------------------------------------
248 * Port configuration
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_PACNT 0x00000000
251#define CONFIG_SYS_PADDR 0x0000
252#define CONFIG_SYS_PADAT 0x0000
253#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
254#define CONFIG_SYS_PBDDR 0x0000
255#define CONFIG_SYS_PBDAT 0x0000
256#define CONFIG_SYS_PDCNT 0x00000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500257#endif /* _M5272C3_H */