blob: 1f53ddcf94d1c3e72679a04b19c016ad6e553221 [file] [log] [blame]
Stefan Roese5e4b3362005-08-22 17:51:53 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22
23 */
24
25/*************************************************************************
26 * (c) 2005 esd gmbh Hannover
27 *
28 *
29 * from IceCube.h file
30 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
31 *
32 *************************************************************************/
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41
42#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
43#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
44#define CONFIG_ICECUBE 1 /* ... on IceCube board */
45#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */
46#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
47
48#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
49
50#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
51#define BOOTFLAG_WARM 0x02 /* Software reboot */
52
Becky Bruce31d82672008-05-08 19:02:12 -050053#define CONFIG_HIGH_BATS 1 /* High BATs supported */
54
Stefan Roese5e4b3362005-08-22 17:51:53 +020055/*
56 * Serial console configuration
57 */
58#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
59#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
60#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
61
62#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
63/*
64 * PCI Mapping:
65 * 0x40000000 - 0x4fffffff - PCI Memory
66 * 0x50000000 - 0x50ffffff - PCI IO Space
67 */
68#if 1
69#define CONFIG_PCI 1
70#if 1
71#define CONFIG_PCI_PNP 1
72#endif
73#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050074#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Stefan Roese5e4b3362005-08-22 17:51:53 +020075
76#define CONFIG_PCI_MEM_BUS 0x40000000
77#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
78#define CONFIG_PCI_MEM_SIZE 0x10000000
79
80#define CONFIG_PCI_IO_BUS 0x50000000
81#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
82#define CONFIG_PCI_IO_SIZE 0x01000000
83#endif
Marian Balakowicz63ff0042005-10-28 22:30:33 +020084
85#define CONFIG_MII
Stefan Roese5e4b3362005-08-22 17:51:53 +020086#if 0 /* test-only !!! */
87#define CONFIG_NET_MULTI 1
88#define CONFIG_EEPRO100 1
89#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
90#define CONFIG_NS8382X 1
91#endif
92
Stefan Roese5e4b3362005-08-22 17:51:53 +020093#endif
94
95/* Partitions */
96#define CONFIG_MAC_PARTITION
97#define CONFIG_DOS_PARTITION
98
99/* USB */
100#if 0
101#define CONFIG_USB_OHCI
Stefan Roese5e4b3362005-08-22 17:51:53 +0200102#define CONFIG_USB_STORAGE
Stefan Roese5e4b3362005-08-22 17:51:53 +0200103#endif
104
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500105/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500106 * BOOTP options
107 */
108#define CONFIG_BOOTP_BOOTFILESIZE
109#define CONFIG_BOOTP_BOOTPATH
110#define CONFIG_BOOTP_GATEWAY
111#define CONFIG_BOOTP_HOSTNAME
112
113
114/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500115 * Command line configuration.
116 */
117#include <config_cmd_default.h>
118
119#if defined(CONFIG_PCI)
120#define CONFIG_CMD_PCI
121#endif
122
123#define CONFIG_CMD_EEPROM
124#define CONFIG_CMD_FAT
125#define CONFIG_CMD_IDE
126#define CONFIG_CMD_I2C
127#define CONFIG_CMD_BSP
128#define CONFIG_CMD_ELF
129#define CONFIG_CMD_EXT2
130#define CONFIG_CMD_DATE
131
Stefan Roese5e4b3362005-08-22 17:51:53 +0200132#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
133# define CFG_LOWBOOT 1
134# define CFG_LOWBOOT16 1
135#endif
136#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
137# define CFG_LOWBOOT 1
138# define CFG_LOWBOOT08 1
139#endif
140
141/*
142 * Autobooting
143 */
144#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
145
146#define CONFIG_PREBOOT "echo;" \
147 "echo Welcome to esd CPU CPCI/5200;" \
148 "echo"
149
150#undef CONFIG_BOOTARGS
151
152#define CONFIG_EXTRA_ENV_SETTINGS \
153 "netdev=eth0\0" \
154 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
155 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100156 "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
157 "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
158 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
Stefan Roese5e4b3362005-08-22 17:51:53 +0200159 "loadaddr=01000000\0" \
160 "serverip=192.168.2.99\0" \
161 "gatewayip=10.0.0.79\0" \
162 "user=mu\0" \
163 "target=cpci5200.esd\0" \
164 "script=cpci5200.bat\0" \
165 "image=/tftpboot/vxWorks_cpci5200\0" \
166 "ipaddr=10.0.13.196\0" \
167 "netmask=255.255.0.0\0" \
168 ""
169
170#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
171
172#if defined(CONFIG_MPC5200)
173
174#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
175#define CFG_NVRAM_BASE_ADDR 0xfd010000
176#define CFG_NVRAM_SIZE 32*1024
177
178/*
179 * IPB Bus clocking configuration.
180 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200181#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200182#endif
183/*
184 * I2C configuration
185 */
186#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
187#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
188
189#define CFG_I2C_SPEED 86000 /* 100 kHz */
190#define CFG_I2C_SLAVE 0x7F
191
192/*
193 * EEPROM configuration
194 */
195#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
196#define CFG_I2C_EEPROM_ADDR_LEN 2
197#define CFG_EEPROM_PAGE_WRITE_BITS 5
198#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
199#define CFG_I2C_MULTI_EEPROMS 1
200/*
201 * Flash configuration
202 */
203
204#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
205#define CFG_FLASH_BASE 0xFE000000
206#define CFG_FLASH_SIZE 0x02000000
207#define CFG_FLASH_INCREMENT 0x01000000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200208#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200209#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
210#define CFG_MAX_FLASH_SECT 128
211
212#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
213#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
214
215#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
216#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
217
218/*
219 * Environment settings
220 */
221#if 1 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200222#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200223#define CONFIG_ENV_SIZE 0x20000
224#define CONFIG_ENV_SECT_SIZE 0x20000
Stefan Roese5e4b3362005-08-22 17:51:53 +0200225#define CONFIG_ENV_OVERWRITE 1
226#else
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200227#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200228#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
229#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200230 /* total size of a CAT24WC32 is 8192 bytes */
231#define CONFIG_ENV_OVERWRITE 1
232#endif
233
234/*
235 * Memory map
236 */
237#define CFG_MBAR 0xF0000000
238#define CFG_SDRAM_BASE 0x00000000
239#define CFG_DEFAULT_MBAR 0x80000000
240
241/* Use SRAM until RAM will be available */
242#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
243#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
244
245#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
246#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
247#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
248
249#define CFG_MONITOR_BASE TEXT_BASE
250#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
251# define CFG_RAMBOOT 1
252#endif
253
254#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
255#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
256#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
257
258/*
259 * Ethernet configuration
260 */
261#define CONFIG_MPC5xxx_FEC 1
262/*
263 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
264 */
265/* #define CONFIG_FEC_10MBIT 1 */
266#define CONFIG_PHY_ADDR 0x00
267#define CONFIG_UDP_CHECKSUM 1
268
269/*
270 * GPIO configuration
271 */
272#define CFG_GPS_PORT_CONFIG 0x01052444
273
274/*
275 * Miscellaneous configurable options
276 */
277#define CFG_LONGHELP /* undef to save memory */
278#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500279#if defined(CONFIG_CMD_KGDB)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200280#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
281#else
282#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
283#endif
284#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
285#define CFG_MAXARGS 16 /* max number of command args */
286#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
287
288#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
289#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
290
291#define CFG_LOAD_ADDR 0x100000 /* default load address */
292
293#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
294
295#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
296
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500297#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
298#if defined(CONFIG_CMD_KGDB)
299# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
300#endif
301
Stefan Roese5e4b3362005-08-22 17:51:53 +0200302/*
303 * Various low-level settings
304 */
305#if defined(CONFIG_MPC5200)
306#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
307#define CFG_HID0_FINAL HID0_ICE
308#else
309#define CFG_HID0_INIT 0
310#define CFG_HID0_FINAL 0
311#endif
312
313#define CFG_BOOTCS_START CFG_FLASH_BASE
314#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
315#define CFG_BOOTCS_CFG 0x0004DD00
316
317#define CFG_CS0_START CFG_FLASH_BASE
318#define CFG_CS0_SIZE CFG_FLASH_SIZE
319
320#define CFG_CS1_START 0xfd000000
321#define CFG_CS1_SIZE 0x00010000
322#define CFG_CS1_CFG 0x10101410
323
324#define CFG_CS3_START 0xfd010000
325#define CFG_CS3_SIZE 0x00010000
326#define CFG_CS3_CFG 0x10109410
327
328#define CFG_CS_BURST 0x00000000
329#define CFG_CS_DEADCYCLE 0x33333333
330
331#define CFG_RESET_ADDRESS 0xff000000
332
333/*-----------------------------------------------------------------------
334 * USB stuff
335 *-----------------------------------------------------------------------
336 */
337#define CONFIG_USB_CLOCK 0x0001BBBB
338#define CONFIG_USB_CONFIG 0x00001000
339
340/*-----------------------------------------------------------------------
341 * IDE/ATA stuff Supports IDE harddisk
342 *-----------------------------------------------------------------------
343 */
344
345#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
346
347#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
348#undef CONFIG_IDE_LED /* LED for ide not supported */
349
350#define CONFIG_IDE_RESET /* reset for ide supported */
351#define CONFIG_IDE_PREINIT
352
353#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
354#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
355
356#define CFG_ATA_IDE0_OFFSET 0x0000
357
358#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
359
360/* Offset for data I/O */
361#define CFG_ATA_DATA_OFFSET (0x0060)
362
363/* Offset for normal register accesses */
364#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
365
366/* Offset for alternate registers */
367#define CFG_ATA_ALT_OFFSET (0x005C)
368
369/* Interval between registers */
370#define CFG_ATA_STRIDE 4
371
372/*-----------------------------------------------------------------------
373 * CPLD stuff
374 */
375#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
376#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
377
378/* CPLD program pin configuration */
379#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
380#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
381#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
382#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
383
384#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
385#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
386#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
387#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
388
389#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00)
390#define JTAG_GPIO_CFG_SET 0x00000000
391#define JTAG_GPIO_CFG_RESET 0x00F00000
392
393#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04)
394#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
395#define JTAG_GPIO_TMS_EN_RESET 0x00000000
396#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C)
397#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
398#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
399
400#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00)
401#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
402#define JTAG_GPIO_TCK_EN_RESET 0x00000000
403#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08)
404#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
405#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
406
407#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00)
408#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
409#define JTAG_GPIO_TDI_EN_RESET 0x00000000
410#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08)
411#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
412#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
413
414#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04)
415#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
416#define JTAG_GPIO_TDO_EN_RESET 0x00000000
417#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C)
418#define JTAG_GPIO_TDO_DDR_SET 0x00000000
419#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
420
421#endif /* __CONFIG_H */