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Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR X11
Gong Qianyu630532f2015-11-11 17:58:38 +08002/*
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 *
5 * Copyright (C) 2015, Freescale Semiconductor
6 *
7 * Mingkai Hu <Mingkai.hu@freescale.com>
Gong Qianyu630532f2015-11-11 17:58:38 +08008 */
9
Gong Qianyu630532f2015-11-11 17:58:38 +080010/include/ "fsl-ls1043a.dtsi"
11
12/ {
13 model = "LS1043A QDS Board";
Qianyu Gong73a5de42016-02-01 13:09:16 +080014 aliases {
15 spi0 = &qspi;
16 spi1 = &dspi0;
17 };
18};
19
20&dspi0 {
21 bus-num = <0>;
22 status = "okay";
23
24 dflash0: n25q128a {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "spi-flash";
Qianyu Gong73a5de42016-02-01 13:09:16 +080028 spi-max-frequency = <1000000>; /* input clock */
Qianyu Gong2ef846e2016-03-23 19:11:36 +080029 spi-cpol;
30 spi-cpha;
31 reg = <0>;
Qianyu Gong73a5de42016-02-01 13:09:16 +080032 };
33
34 dflash1: sst25wf040b {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "spi-flash";
38 spi-max-frequency = <3500000>;
Qianyu Gong2ef846e2016-03-23 19:11:36 +080039 spi-cpol;
40 spi-cpha;
Qianyu Gong73a5de42016-02-01 13:09:16 +080041 reg = <1>;
42 };
43
44 dflash2: en25s64 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "spi-flash";
48 spi-max-frequency = <3500000>;
Qianyu Gong2ef846e2016-03-23 19:11:36 +080049 spi-cpol;
50 spi-cpha;
Qianyu Gong73a5de42016-02-01 13:09:16 +080051 reg = <2>;
52 };
53};
54
55&qspi {
56 bus-num = <0>;
57 status = "okay";
58
59 qflash0: s25fl128s@0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "spi-flash";
63 spi-max-frequency = <20000000>;
64 reg = <0>;
65 };
Gong Qianyu630532f2015-11-11 17:58:38 +080066};
67
68&i2c0 {
69 status = "okay";
70 pca9547@77 {
71 compatible = "philips,pca9547";
72 reg = <0x77>;
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 i2c@0 {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 reg = <0x0>;
80
81 rtc@68 {
82 compatible = "dallas,ds3232";
83 reg = <0x68>;
84 /* IRQ10_B */
85 interrupts = <0 150 0x4>;
86 };
87 };
88
89 i2c@2 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 reg = <0x2>;
93
94 ina220@40 {
95 compatible = "ti,ina220";
96 reg = <0x40>;
97 shunt-resistor = <1000>;
98 };
99
100 ina220@41 {
101 compatible = "ti,ina220";
102 reg = <0x41>;
103 shunt-resistor = <1000>;
104 };
105 };
106
107 i2c@3 {
108 #address-cells = <1>;
109 #size-cells = <0>;
110 reg = <0x3>;
111
112 eeprom@56 {
113 compatible = "at24,24c512";
114 reg = <0x56>;
115 };
116
117 eeprom@57 {
118 compatible = "at24,24c512";
119 reg = <0x57>;
120 };
121
122 adt7461a@4c {
123 compatible = "adt7461a";
124 reg = <0x4c>;
125 };
126 };
127 };
128};
129
130&ifc {
131 #address-cells = <2>;
132 #size-cells = <1>;
133 /* NOR, NAND Flashes and FPGA on board */
134 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
Hou Zhiqiang4002eab2016-12-06 15:27:49 +0800135 0x1 0x0 0x0 0x7e800000 0x00010000
136 0x2 0x0 0x0 0x7fb00000 0x00000100>;
Gong Qianyu630532f2015-11-11 17:58:38 +0800137 status = "okay";
138
139 nor@0,0 {
140 #address-cells = <1>;
141 #size-cells = <1>;
142 compatible = "cfi-flash";
143 reg = <0x0 0x0 0x8000000>;
144 bank-width = <2>;
145 device-width = <1>;
146 };
147
Hou Zhiqiang4002eab2016-12-06 15:27:49 +0800148 nand@1,0 {
Gong Qianyu630532f2015-11-11 17:58:38 +0800149 compatible = "fsl,ifc-nand";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 reg = <0x1 0x0 0x10000>;
153 };
154
Hou Zhiqiang4002eab2016-12-06 15:27:49 +0800155 fpga: board-control@2,0 {
Gong Qianyu630532f2015-11-11 17:58:38 +0800156 #address-cells = <1>;
157 #size-cells = <1>;
158 compatible = "simple-bus";
Hou Zhiqiang4002eab2016-12-06 15:27:49 +0800159 reg = <0x2 0x0 0x0000100>;
Gong Qianyu630532f2015-11-11 17:58:38 +0800160 bank-width = <1>;
161 device-width = <1>;
Hou Zhiqiang4002eab2016-12-06 15:27:49 +0800162 ranges = <0 2 0 0x100>;
Gong Qianyu630532f2015-11-11 17:58:38 +0800163 };
164};
165
166&duart0 {
167 status = "okay";
168};
169
170&duart1 {
171 status = "okay";
172};
Wenbin Song2970e142016-01-21 17:14:55 +0800173
174&lpuart0 {
175 status = "okay";
176};
Peng Mad9211652018-08-01 11:35:14 +0800177
178&sata {
179 status = "okay";
180};