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stroese22a40b02003-09-12 08:42:13 +00001/*
stroesecd5396f2004-12-16 18:41:27 +00002 * (C) Copyright 2001-2004
stroese22a40b02003-09-12 08:42:13 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +010025#include <asm/io.h>
stroese22a40b02003-09-12 08:42:13 +000026#include <asm/processor.h>
27#include <command.h>
28#include <malloc.h>
29
30/* ------------------------------------------------------------------------- */
31
32#if 0
33#define FPGA_DEBUG
34#endif
35
36extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
stroesecd5396f2004-12-16 18:41:27 +000037extern void lxt971_no_sleep(void);
stroese22a40b02003-09-12 08:42:13 +000038
39/* fpga configuration data - gzip compressed and generated by bin2c */
40const unsigned char fpgadata[] =
41{
42#include "fpgadata.c"
43};
44
45/*
46 * include common fpga code (for esd boards)
47 */
48#include "../common/fpga.c"
49
50
stroesecd5396f2004-12-16 18:41:27 +000051/* logo bitmap data - gzip compressed and generated by bin2c */
52unsigned char logo_bmp_320[] =
53{
54#include "logo_320_240_4bpp.c"
55};
56
57unsigned char logo_bmp_640[] =
58{
59#include "logo_640_480_24bpp.c"
60};
61
62
63/*
64 * include common lcd code (for esd boards)
65 */
66#include "../common/lcd.c"
67
68#include "../common/s1d13704_320_240_4bpp.h"
69#include "../common/s1d13806_320_240_4bpp.h"
70#include "../common/s1d13806_640_480_16bpp.h"
71
72
wdenkc837dcb2004-01-20 23:12:12 +000073int board_early_init_f (void)
stroese22a40b02003-09-12 08:42:13 +000074{
75 /*
76 * IRQ 0-15 405GP internally generated; active high; level sensitive
77 * IRQ 16 405GP internally generated; active low; level sensitive
78 * IRQ 17-24 RESERVED
79 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
80 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
81 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
82 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
83 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
84 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
85 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
86 */
Stefan Roese952e7762009-09-24 09:55:50 +020087 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
88 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
89 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
90 mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */
91 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
92 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
93 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
stroese22a40b02003-09-12 08:42:13 +000094
95 /*
96 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
97 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020098 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
stroese22a40b02003-09-12 08:42:13 +000099
100 return 0;
101}
102
stroese22a40b02003-09-12 08:42:13 +0000103int misc_init_r (void)
104{
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100105 unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
106 unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
107 unsigned short *lcd_contrast =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108 (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100109 unsigned short *lcd_backlight =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110 (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
stroese22a40b02003-09-12 08:42:13 +0000111 unsigned char *dst;
112 ulong len = sizeof(fpgadata);
113 int status;
114 int index;
115 int i;
stroesecd5396f2004-12-16 18:41:27 +0000116 char *str;
stroese22a40b02003-09-12 08:42:13 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
119 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
stroese22a40b02003-09-12 08:42:13 +0000120 printf ("GUNZIP ERROR - must RESET board to recover\n");
121 do_reset (NULL, 0, 0, NULL);
122 }
123
124 status = fpga_boot(dst, len);
125 if (status != 0) {
126 printf("\nFPGA: Booting failed ");
127 switch (status) {
128 case ERROR_FPGA_PRG_INIT_LOW:
129 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
130 break;
131 case ERROR_FPGA_PRG_INIT_HIGH:
132 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
133 break;
134 case ERROR_FPGA_PRG_DONE:
135 printf("(Timeout: DONE not high after programming FPGA)\n ");
136 break;
137 }
138
139 /* display infos on fpgaimage */
140 index = 15;
141 for (i=0; i<4; i++) {
142 len = dst[index];
143 printf("FPGA: %s\n", &(dst[index+1]));
144 index += len+3;
145 }
146 putc ('\n');
147 /* delayed reboot */
148 for (i=20; i>0; i--) {
149 printf("Rebooting in %2d seconds \r",i);
150 for (index=0;index<1000;index++)
151 udelay(1000);
152 }
153 putc ('\n');
154 do_reset(NULL, 0, 0, NULL);
155 }
156
157 puts("FPGA: ");
158
159 /* display infos on fpgaimage */
160 index = 15;
161 for (i=0; i<4; i++) {
162 len = dst[index];
163 printf("%s ", &(dst[index+1]));
164 index += len+3;
165 }
166 putc ('\n');
167
168 free(dst);
169
170 /*
stroesecd5396f2004-12-16 18:41:27 +0000171 * Reset FPGA via FPGA_INIT pin
stroese22a40b02003-09-12 08:42:13 +0000172 */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100173 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
174 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
stroese22a40b02003-09-12 08:42:13 +0000175 udelay(1000); /* wait 1ms */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100176 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
stroese22a40b02003-09-12 08:42:13 +0000177 udelay(1000); /* wait 1ms */
178
179 /*
180 * Reset external DUARTs
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
stroese22a40b02003-09-12 08:42:13 +0000183 udelay(10); /* wait 10us */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
stroese22a40b02003-09-12 08:42:13 +0000185 udelay(1000); /* wait 1ms */
186
187 /*
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100188 * Set NAND-FLASH GPIO signals to default
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
191 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100192
193 /*
194 * Setup EEPROM write protection
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
197 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100198
199 /*
stroese22a40b02003-09-12 08:42:13 +0000200 * Enable interrupts in exar duart mcr[3]
201 */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100202 out_8(duart0_mcr, 0x08);
203 out_8(duart1_mcr, 0x08);
stroese22a40b02003-09-12 08:42:13 +0000204
205 /*
stroesecd5396f2004-12-16 18:41:27 +0000206 * Init lcd interface and display logo
207 */
208 str = getenv("bd_type");
209 if (strcmp(str, "voh405_bw") == 0) {
210 lcd_setup(0, 1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
stroesecd5396f2004-12-16 18:41:27 +0000212 regs_13704_320_240_4bpp,
213 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
214 logo_bmp_320, sizeof(logo_bmp_320));
215 } else if (strcmp(str, "voh405_bwbw") == 0) {
216 lcd_setup(0, 1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
stroesecd5396f2004-12-16 18:41:27 +0000218 regs_13704_320_240_4bpp,
219 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
220 logo_bmp_320, sizeof(logo_bmp_320));
221 lcd_setup(1, 1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
stroesecd5396f2004-12-16 18:41:27 +0000223 regs_13806_320_240_4bpp,
224 sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
225 logo_bmp_320, sizeof(logo_bmp_320));
226 } else if (strcmp(str, "voh405_bwc") == 0) {
227 lcd_setup(0, 1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
stroesecd5396f2004-12-16 18:41:27 +0000229 regs_13704_320_240_4bpp,
230 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
231 logo_bmp_320, sizeof(logo_bmp_320));
232 lcd_setup(1, 0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
stroesecd5396f2004-12-16 18:41:27 +0000234 regs_13806_640_480_16bpp,
235 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
236 logo_bmp_640, sizeof(logo_bmp_640));
237 } else {
238 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
239 return 0;
240 }
241
242 /*
243 * Set invert bit in small lcd controller
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245 out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
246 in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
stroesecd5396f2004-12-16 18:41:27 +0000247
248 /*
stroese22a40b02003-09-12 08:42:13 +0000249 * Set default contrast voltage on epson vga controller
250 */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100251 out_be16(lcd_contrast, 0x4646);
stroesecd5396f2004-12-16 18:41:27 +0000252
253 /*
254 * Enable backlight
255 */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100256 out_be16(lcd_backlight, 0xffff);
257
258 /*
259 * Enable external I2C bus
260 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
stroese22a40b02003-09-12 08:42:13 +0000262
263 return (0);
264}
265
266
267/*
268 * Check Board Identity:
269 */
270
271int checkboard (void)
272{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200273 char str[64];
stroese22a40b02003-09-12 08:42:13 +0000274 int i = getenv_r ("serial#", str, sizeof(str));
275
276 puts ("Board: ");
277
278 if (i == -1) {
279 puts ("### No HW ID - assuming VOH405");
280 } else {
281 puts(str);
282 }
283
stroesecd5396f2004-12-16 18:41:27 +0000284 if (getenv_r("bd_type", str, sizeof(str)) != -1) {
285 printf(" (%s)", str);
286 } else {
287 puts(" (Missing bd_type!)");
288 }
289
stroese22a40b02003-09-12 08:42:13 +0000290 putc ('\n');
291
stroese22a40b02003-09-12 08:42:13 +0000292 return 0;
293}
294
stroese22a40b02003-09-12 08:42:13 +0000295#ifdef CONFIG_IDE_RESET
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100296#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
stroese22a40b02003-09-12 08:42:13 +0000297void ide_set_reset(int on)
298{
stroese22a40b02003-09-12 08:42:13 +0000299 /*
300 * Assert or deassert CompactFlash Reset Pin
301 */
302 if (on) { /* assert RESET */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100303 out_be16((void *)FPGA_MODE,
304 in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
stroese22a40b02003-09-12 08:42:13 +0000305 } else { /* release RESET */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100306 out_be16((void *)FPGA_MODE,
307 in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
stroese22a40b02003-09-12 08:42:13 +0000308 }
309}
310#endif /* CONFIG_IDE_RESET */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100311
312#if defined(CONFIG_RESET_PHY_R)
313void reset_phy(void)
314{
315#ifdef CONFIG_LXT971_NO_SLEEP
316
317 /*
318 * Disable sleep mode in LXT971
319 */
320 lxt971_no_sleep();
321#endif
322}
323#endif
324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#if defined(CONFIG_SYS_EEPROM_WREN)
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100326/* Input: <dev_addr> I2C address of EEPROM device to enable.
327 * <state> -1: deliver current state
328 * 0: disable write
329 * 1: enable write
330 * Returns: -1: wrong device address
331 * 0: dis-/en- able done
332 * 0/1: current state if <state> was -1.
333 */
334int eeprom_write_enable (unsigned dev_addr, int state)
335{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100337 return -1;
338 } else {
339 switch (state) {
340 case 1:
341 /* Enable write access, clear bit GPIO0. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100343 state = 0;
344 break;
345 case 0:
346 /* Disable write access, set bit GPIO0. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100348 state = 0;
349 break;
350 default:
351 /* Read current status back. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352 state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100353 break;
354 }
355 }
356 return state;
357}
358
359int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
360{
361 int query = argc == 1;
362 int state = 0;
363
364 if (query) {
365 /* Query write access state. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100367 if (state < 0) {
368 puts ("Query of write access state failed.\n");
369 } else {
370 printf ("Write access for device 0x%0x is %sabled.\n",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100372 state = 0;
373 }
374 } else {
375 if ('0' == argv[1][0]) {
376 /* Disable write access. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100378 } else {
379 /* Enable write access. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100381 }
382 if (state < 0) {
383 puts ("Setup of write access state failed.\n");
384 }
385 }
386
387 return state;
388}
389
390U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200391 "Enable / disable / query EEPROM write access",
392 ""
393);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */