blob: 34e88a8f2ee1ec85021c6ac122c3c6c353d7b104 [file] [log] [blame]
Matt Waddelb80e41a2010-10-07 15:48:45 -06001/*
2 * (C) Copyright 2010 Linaro
3 * Matt Waddel, <matt.waddel@linaro.org>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Matt Waddelb80e41a2010-10-07 15:48:45 -06006 */
7#ifndef _SYSCTRL_H_
8#define _SYSCTRL_H_
9
10/* System controller (SP810) register definitions */
11#define SP810_TIMER0_ENSEL (1 << 15)
12#define SP810_TIMER1_ENSEL (1 << 17)
13#define SP810_TIMER2_ENSEL (1 << 19)
14#define SP810_TIMER3_ENSEL (1 << 21)
15
16struct sysctrl {
17 u32 scctrl; /* 0x000 */
18 u32 scsysstat;
19 u32 scimctrl;
20 u32 scimstat;
21 u32 scxtalctrl;
22 u32 scpllctrl;
23 u32 scpllfctrl;
24 u32 scperctrl0;
25 u32 scperctrl1;
26 u32 scperen;
27 u32 scperdis;
28 u32 scperclken;
29 u32 scperstat;
30 u32 res1[0x006];
31 u32 scflashctrl; /* 0x04c */
32 u32 res2[0x3a4];
33 u32 scsysid0; /* 0xee0 */
34 u32 scsysid1;
35 u32 scsysid2;
36 u32 scsysid3;
37 u32 scitcr;
38 u32 scitir0;
39 u32 scitir1;
40 u32 scitor;
41 u32 sccntctrl;
42 u32 sccntdata;
43 u32 sccntstep;
44 u32 res3[0x32];
45 u32 scperiphid0; /* 0xfe0 */
46 u32 scperiphid1;
47 u32 scperiphid2;
48 u32 scperiphid3;
49 u32 scpcellid0;
50 u32 scpcellid1;
51 u32 scpcellid2;
52 u32 scpcellid3;
53};
54#endif /* _SYSCTRL_H_ */