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Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +01001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +01004 * Lead Tech Design <www.leadtechdesign.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +01007 */
8
9#include <common.h>
Asen Dimov3ad24802011-07-26 01:23:39 +000010#include <asm/io.h>
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010011#include <asm/arch/at91_common.h>
Wenyou Yangeced5a72016-02-03 10:16:49 +080012#include <asm/arch/clk.h>
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010013#include <asm/arch/gpio.h>
Asen Dimov3ad24802011-07-26 01:23:39 +000014
15/*
16 * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
17 * peripheral pins. Good to have if hardware is soldered optionally
18 * or in case of SPI no slave is selected. Avoid lines to float
19 * needlessly. Use a short local PUP define.
20 *
21 * Due to errata "TXD floats when CTS is inactive" pullups are always
22 * on for TXD pins.
23 */
24#ifdef CONFIG_AT91_GPIO_PULLUP
25# define PUP CONFIG_AT91_GPIO_PULLUP
26#else
27# define PUP 0
28#endif
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010029
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020030void at91_serial0_hw_init(void)
31{
Jens Scharsig7f9e8632010-02-03 22:46:46 +010032 at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */
33 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */
Wenyou Yangeced5a72016-02-03 10:16:49 +080034 at91_periph_clk_enable(ATMEL_ID_USART0);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020035}
36
37void at91_serial1_hw_init(void)
38{
Jens Scharsig7f9e8632010-02-03 22:46:46 +010039 at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
40 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
Wenyou Yangeced5a72016-02-03 10:16:49 +080041 at91_periph_clk_enable(ATMEL_ID_USART1);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020042}
43
44void at91_serial2_hw_init(void)
45{
Jens Scharsig7f9e8632010-02-03 22:46:46 +010046 at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
47 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
Wenyou Yangeced5a72016-02-03 10:16:49 +080048 at91_periph_clk_enable(ATMEL_ID_USART2);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020049}
50
Asen Dimov3ad24802011-07-26 01:23:39 +000051void at91_seriald_hw_init(void)
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020052{
Jens Scharsig7f9e8632010-02-03 22:46:46 +010053 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
54 at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
Wenyou Yangeced5a72016-02-03 10:16:49 +080055 at91_periph_clk_enable(ATMEL_ID_SYS);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020056}
57
Asen Dimov3ad24802011-07-26 01:23:39 +000058#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010059void at91_spi0_hw_init(unsigned long cs_mask)
60{
Asen Dimov3ad24802011-07-26 01:23:39 +000061 at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
62 at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
63 at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010064
Wenyou Yangeced5a72016-02-03 10:16:49 +080065 at91_periph_clk_enable(ATMEL_ID_SPI0);
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010066
67 if (cs_mask & (1 << 0)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010068 at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010069 }
70 if (cs_mask & (1 << 1)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010071 at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010072 }
73 if (cs_mask & (1 << 2)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010074 at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010075 }
76 if (cs_mask & (1 << 3)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010077 at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
Jean-Christophe PLAGNIOL-VILLARDa47492a2009-03-27 13:14:52 +010078 }
79 if (cs_mask & (1 << 4)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010080 at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
Jean-Christophe PLAGNIOL-VILLARDa47492a2009-03-27 13:14:52 +010081 }
82 if (cs_mask & (1 << 5)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010083 at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
Jean-Christophe PLAGNIOL-VILLARDa47492a2009-03-27 13:14:52 +010084 }
85 if (cs_mask & (1 << 6)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010086 at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
Jean-Christophe PLAGNIOL-VILLARDa47492a2009-03-27 13:14:52 +010087 }
88 if (cs_mask & (1 << 7)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010089 at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010090 }
91}
92
93void at91_spi1_hw_init(unsigned long cs_mask)
94{
Asen Dimov3ad24802011-07-26 01:23:39 +000095 at91_set_a_periph(AT91_PIO_PORTB, 30, PUP); /* SPI1_MISO */
96 at91_set_a_periph(AT91_PIO_PORTB, 31, PUP); /* SPI1_MOSI */
97 at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* SPI1_SPCK */
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +010098
Wenyou Yangeced5a72016-02-03 10:16:49 +080099 at91_periph_clk_enable(ATMEL_ID_SPI1);
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100100
101 if (cs_mask & (1 << 0)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +0100102 at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100103 }
104 if (cs_mask & (1 << 1)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +0100105 at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100106 }
107 if (cs_mask & (1 << 2)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +0100108 at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100109 }
110 if (cs_mask & (1 << 3)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +0100111 at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
Jean-Christophe PLAGNIOL-VILLARDa47492a2009-03-27 13:14:52 +0100112 }
113 if (cs_mask & (1 << 4)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +0100114 at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
Jean-Christophe PLAGNIOL-VILLARDa47492a2009-03-27 13:14:52 +0100115 }
116 if (cs_mask & (1 << 5)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +0100117 at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
Jean-Christophe PLAGNIOL-VILLARDa47492a2009-03-27 13:14:52 +0100118 }
119 if (cs_mask & (1 << 6)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +0100120 at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
Jean-Christophe PLAGNIOL-VILLARDa47492a2009-03-27 13:14:52 +0100121 }
122 if (cs_mask & (1 << 7)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +0100123 at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100124 }
125}
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +0200126#endif