| Stefan Roese | 2a61eff | 2009-01-21 17:25:01 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering |
| 3 | * |
| 4 | * Copyright (C) 2006 Micronas GmbH |
| 5 | * |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| Stefan Roese | 2a61eff | 2009-01-21 17:25:01 +0100 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef _REG_EBI_PLATINUMAVC_H_ |
| 10 | #define _REG_EBI_PLATINUMAVC_H_ |
| 11 | |
| 12 | #define EBI_BASE 0x00014000 |
| 13 | |
| 14 | /* Relative offsets of the register adresses */ |
| 15 | |
| 16 | #define EBI_CPU_IO_ACCS_OFFS 0x00000000 |
| 17 | #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) |
| 18 | #define EBI_IO_ACCS_DATA_OFFS 0x00000004 |
| 19 | #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) |
| 20 | #define EBI_CPU_IO_ACCS2_OFFS 0x00000008 |
| 21 | #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) |
| 22 | #define EBI_IO_ACCS2_DATA_OFFS 0x0000000C |
| 23 | #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) |
| 24 | #define EBI_CTRL_OFFS 0x00000010 |
| 25 | #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) |
| 26 | #define EBI_IRQ_MASK_OFFS 0x00000018 |
| 27 | #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) |
| 28 | #define EBI_IRQ_MASK2_OFFS 0x0000001C |
| 29 | #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) |
| 30 | #define EBI_TAG1_SYS_ID_OFFS 0x00000030 |
| 31 | #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) |
| 32 | #define EBI_TAG2_SYS_ID_OFFS 0x00000040 |
| 33 | #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) |
| 34 | #define EBI_TAG3_SYS_ID_OFFS 0x00000050 |
| 35 | #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) |
| 36 | #define EBI_TAG4_SYS_ID_OFFS 0x00000060 |
| 37 | #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) |
| 38 | #define EBI_GEN_DMA_CTRL_OFFS 0x00000070 |
| 39 | #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) |
| 40 | #define EBI_STATUS_OFFS 0x00000080 |
| 41 | #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) |
| 42 | #define EBI_STATUS_DMA_CNT_OFFS 0x00000084 |
| 43 | #define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) |
| 44 | #define EBI_SIG_LEVEL_OFFS 0x00000088 |
| 45 | #define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) |
| 46 | #define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C |
| 47 | #define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) |
| 48 | #define EBI_CRC_GEN_OFFS 0x00000090 |
| 49 | #define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS) |
| 50 | #define EBI_EXT_ADDR_OFFS 0x000000A0 |
| 51 | #define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) |
| 52 | #define EBI_IRQ_STATUS_OFFS 0x000000B0 |
| 53 | #define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) |
| 54 | #define EBI_IRQ_STATUS2_OFFS 0x000000B4 |
| 55 | #define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS) |
| 56 | #define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0 |
| 57 | #define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS) |
| 58 | #define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4 |
| 59 | #define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS) |
| 60 | #define EBI_ECC0_OFFS 0x000000D0 |
| 61 | #define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS) |
| 62 | #define EBI_ECC1_OFFS 0x000000D4 |
| 63 | #define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS) |
| 64 | #define EBI_ECC2_OFFS 0x000000D8 |
| 65 | #define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS) |
| 66 | #define EBI_ECC3_OFFS 0x000000DC |
| 67 | #define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS) |
| 68 | #define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 |
| 69 | #define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) |
| 70 | #define EBI_DEV1_EXT_ACC_OFFS 0x00000104 |
| 71 | #define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) |
| 72 | #define EBI_DEV1_CONFIG1_OFFS 0x00000108 |
| 73 | #define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) |
| 74 | #define EBI_DEV1_CONFIG2_OFFS 0x0000010C |
| 75 | #define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) |
| 76 | #define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 |
| 77 | #define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) |
| 78 | #define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 |
| 79 | #define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) |
| 80 | #define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 |
| 81 | #define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) |
| 82 | #define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C |
| 83 | #define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) |
| 84 | #define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120 |
| 85 | #define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS) |
| 86 | #define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 |
| 87 | #define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) |
| 88 | #define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 |
| 89 | #define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) |
| 90 | #define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C |
| 91 | #define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) |
| 92 | #define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 |
| 93 | #define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) |
| 94 | #define EBI_DEV1_TIM_EXT_OFFS 0x00000134 |
| 95 | #define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) |
| 96 | #define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 |
| 97 | #define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) |
| 98 | #define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C |
| 99 | #define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) |
| 100 | #define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 |
| 101 | #define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) |
| 102 | #define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 |
| 103 | #define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) |
| 104 | #define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148 |
| 105 | #define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS) |
| 106 | #define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C |
| 107 | #define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS) |
| 108 | #define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 |
| 109 | #define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) |
| 110 | #define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 |
| 111 | #define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) |
| 112 | #define EBI_DEV2_EXT_ACC_OFFS 0x00000204 |
| 113 | #define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) |
| 114 | #define EBI_DEV2_CONFIG1_OFFS 0x00000208 |
| 115 | #define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) |
| 116 | #define EBI_DEV2_CONFIG2_OFFS 0x0000020C |
| 117 | #define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) |
| 118 | #define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 |
| 119 | #define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) |
| 120 | #define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 |
| 121 | #define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) |
| 122 | #define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 |
| 123 | #define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) |
| 124 | #define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C |
| 125 | #define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) |
| 126 | #define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220 |
| 127 | #define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS) |
| 128 | #define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 |
| 129 | #define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) |
| 130 | #define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 |
| 131 | #define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) |
| 132 | #define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C |
| 133 | #define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) |
| 134 | #define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 |
| 135 | #define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) |
| 136 | #define EBI_DEV2_TIM_EXT_OFFS 0x00000234 |
| 137 | #define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) |
| 138 | #define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 |
| 139 | #define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) |
| 140 | #define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C |
| 141 | #define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) |
| 142 | #define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 |
| 143 | #define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) |
| 144 | #define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 |
| 145 | #define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) |
| 146 | #define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248 |
| 147 | #define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS) |
| 148 | #define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C |
| 149 | #define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS) |
| 150 | #define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 |
| 151 | #define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) |
| 152 | #define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 |
| 153 | #define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) |
| 154 | #define EBI_DEV3_EXT_ACC_OFFS 0x00000304 |
| 155 | #define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) |
| 156 | #define EBI_DEV3_CONFIG1_OFFS 0x00000308 |
| 157 | #define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) |
| 158 | #define EBI_DEV3_CONFIG2_OFFS 0x0000030C |
| 159 | #define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) |
| 160 | #define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 |
| 161 | #define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) |
| 162 | #define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 |
| 163 | #define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) |
| 164 | #define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 |
| 165 | #define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) |
| 166 | #define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C |
| 167 | #define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) |
| 168 | #define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320 |
| 169 | #define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS) |
| 170 | #define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 |
| 171 | #define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) |
| 172 | #define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 |
| 173 | #define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) |
| 174 | #define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C |
| 175 | #define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) |
| 176 | #define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 |
| 177 | #define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) |
| 178 | #define EBI_DEV3_TIM_EXT_OFFS 0x00000334 |
| 179 | #define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) |
| 180 | #define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 |
| 181 | #define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) |
| 182 | #define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C |
| 183 | #define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) |
| 184 | #define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 |
| 185 | #define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) |
| 186 | #define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 |
| 187 | #define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) |
| 188 | #define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348 |
| 189 | #define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS) |
| 190 | #define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C |
| 191 | #define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS) |
| 192 | #define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 |
| 193 | #define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) |
| 194 | #define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 |
| 195 | #define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) |
| 196 | #define EBI_DEV4_EXT_ACC_OFFS 0x00000404 |
| 197 | #define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) |
| 198 | #define EBI_DEV4_CONFIG1_OFFS 0x00000408 |
| 199 | #define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) |
| 200 | #define EBI_DEV4_CONFIG2_OFFS 0x0000040C |
| 201 | #define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) |
| 202 | #define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 |
| 203 | #define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) |
| 204 | #define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 |
| 205 | #define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) |
| 206 | #define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 |
| 207 | #define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) |
| 208 | #define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C |
| 209 | #define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) |
| 210 | #define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420 |
| 211 | #define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS) |
| 212 | #define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 |
| 213 | #define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) |
| 214 | #define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 |
| 215 | #define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) |
| 216 | #define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C |
| 217 | #define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) |
| 218 | #define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 |
| 219 | #define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) |
| 220 | #define EBI_DEV4_TIM_EXT_OFFS 0x00000434 |
| 221 | #define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) |
| 222 | #define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 |
| 223 | #define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) |
| 224 | #define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C |
| 225 | #define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) |
| 226 | #define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 |
| 227 | #define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) |
| 228 | #define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 |
| 229 | #define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) |
| 230 | #define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448 |
| 231 | #define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS) |
| 232 | #define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C |
| 233 | #define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS) |
| 234 | #define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 |
| 235 | #define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) |
| 236 | #define EBI_INTERLEAVE_CNT_OFFS 0x00000900 |
| 237 | #define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS) |
| 238 | #define EBI_CNT_FL_PROGR_OFFS 0x00000904 |
| 239 | #define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) |
| 240 | #define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C |
| 241 | #define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) |
| 242 | #define EBI_CNT_WAIT_RDY_OFFS 0x00000914 |
| 243 | #define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) |
| 244 | #define EBI_CNT_ACK_OFFS 0x00000918 |
| 245 | #define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) |
| 246 | #define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 |
| 247 | #define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) |
| 248 | #define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 |
| 249 | #define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) |
| 250 | #define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 |
| 251 | #define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) |
| 252 | #define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 |
| 253 | #define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) |
| 254 | #define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 |
| 255 | #define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) |
| 256 | #define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 |
| 257 | #define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) |
| 258 | #define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 |
| 259 | #define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) |
| 260 | #define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 |
| 261 | #define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) |
| 262 | #define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 |
| 263 | #define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) |
| 264 | #define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 |
| 265 | #define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) |
| 266 | #define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 |
| 267 | #define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) |
| 268 | #define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 |
| 269 | #define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) |
| 270 | #define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 |
| 271 | #define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) |
| 272 | #define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 |
| 273 | #define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) |
| 274 | #define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 |
| 275 | #define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) |
| 276 | |
| 277 | #endif |