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gerrit.cesnet.cz / github / trini / u-boot / 0b741df241aa5eba6c9e21b4cfcaa3fe5f57753d / . / include / asm-arm / arch-omap3 / cpu.h
blob: 69c0b368d45a25f668aa70a3434ccdc79453f364 [file] [log] [blame]
Dirk Behme2c803212008-12-14 09:47:11 +0100[diff] [blame]1/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25#ifndef _CPU_H
26#define _CPU_H
27
28/* Register offsets of common modules */
29/* Control */
30#ifndef __ASSEMBLY__
31typedef struct ctrl {
32 unsigned char res1[0xC0];
33 unsigned short gpmc_nadv_ale; /* 0xC0 */
34 unsigned short gpmc_noe; /* 0xC2 */
35 unsigned short gpmc_nwe; /* 0xC4 */
36 unsigned char res2[0x22A];
37 unsigned int status; /* 0x2F0 */
38} ctrl_t;
39#else /* __ASSEMBLY__ */
40#define CONTROL_STATUS 0x2F0
41#endif /* __ASSEMBLY__ */
42
43/* device type */
44#define DEVICE_MASK (0x7 << 8)
45#define SYSBOOT_MASK 0x1F
46#define TST_DEVICE 0x0
47#define EMU_DEVICE 0x1
48#define HS_DEVICE 0x2
49#define GP_DEVICE 0x3
50
51/* GPMC CS3/cs4/cs6 not avaliable */
52#define GPMC_BASE (OMAP34XX_GPMC_BASE)
53#define GPMC_CONFIG_CS0 0x60
54#define GPMC_CONFIG_CS6 0x150
55#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
56#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
57#define GPMC_CONFIG_WP 0x10
58
59#define GPMC_CONFIG_WIDTH 0x30
60
61#ifndef __ASSEMBLY__
62typedef struct gpmc {
63 unsigned char res1[0x10];
64 unsigned int sysconfig; /* 0x10 */
65 unsigned char res2[0x4];
66 unsigned int irqstatus; /* 0x18 */
67 unsigned int irqenable; /* 0x1C */
68 unsigned char res3[0x20];
69 unsigned int timeout_control; /* 0x40 */
70 unsigned char res4[0xC];
71 unsigned int config; /* 0x50 */
72 unsigned int status; /* 0x54 */
73 unsigned char res5[0x19C];
74 unsigned int ecc_config; /* 0x1F4 */
75 unsigned int ecc_control; /* 0x1F8 */
76 unsigned int ecc_size_config; /* 0x1FC */
77 unsigned int ecc1_result; /* 0x200 */
78 unsigned int ecc2_result; /* 0x204 */
79 unsigned int ecc3_result; /* 0x208 */
80 unsigned int ecc4_result; /* 0x20C */
81 unsigned int ecc5_result; /* 0x210 */
82 unsigned int ecc6_result; /* 0x214 */
83 unsigned int ecc7_result; /* 0x218 */
84 unsigned int ecc8_result; /* 0x21C */
85 unsigned int ecc9_result; /* 0x220 */
86} gpmc_t;
87
88typedef struct gpmc_csx {
89 unsigned int config1; /* 0x00 */
90 unsigned int config2; /* 0x04 */
91 unsigned int config3; /* 0x08 */
92 unsigned int config4; /* 0x0C */
93 unsigned int config5; /* 0x10 */
94 unsigned int config6; /* 0x14 */
95 unsigned int config7; /* 0x18 */
96 unsigned int nand_cmd; /* 0x1C */
97 unsigned int nand_adr; /* 0x20 */
98 unsigned int nand_dat; /* 0x24 */
99} gpmc_csx_t;
100#else /* __ASSEMBLY__ */
101#define GPMC_CONFIG1 0x00
102#define GPMC_CONFIG2 0x04
103#define GPMC_CONFIG3 0x08
104#define GPMC_CONFIG4 0x0C
105#define GPMC_CONFIG5 0x10
106#define GPMC_CONFIG6 0x14
107#define GPMC_CONFIG7 0x18
108#endif /* __ASSEMBLY__ */
109
110/* GPMC Mapping */
111#define FLASH_BASE 0x10000000 /* NOR flash, */
112 /* aligned to 256 Meg */
113#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
114 /* aligned to 64 Meg */
115#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
116 /* aligned to 256 Meg */
117#define DEBUG_BASE 0x08000000 /* debug board */
118#define NAND_BASE 0x30000000 /* NAND addr */
119 /* (actual size small port) */
120#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
121#define ONENAND_MAP 0x20000000 /* OneNand addr */
122 /* (actual size small port) */
123/* SMS */
124#ifndef __ASSEMBLY__
125typedef struct sms {
126 unsigned char res1[0x10];
127 unsigned int sysconfig; /* 0x10 */
128 unsigned char res2[0x34];
129 unsigned int rg_att0; /* 0x48 */
130 unsigned char res3[0x84];
131 unsigned int class_arb0; /* 0xD0 */
132} sms_t;
133#endif /* __ASSEMBLY__ */
134
135#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
136
137/* SDRC */
138#ifndef __ASSEMBLY__
139typedef struct sdrc_cs {
140 unsigned int mcfg; /* 0x80 || 0xB0 */
141 unsigned int mr; /* 0x84 || 0xB4 */
142 unsigned char res1[0x4];
143 unsigned int emr2; /* 0x8C || 0xBC */
144 unsigned char res2[0x14];
145 unsigned int rfr_ctrl; /* 0x84 || 0xD4 */
146 unsigned int manual; /* 0xA8 || 0xD8 */
147 unsigned char res3[0x4];
148} sdrc_cs_t;
149
150typedef struct sdrc_actim {
151 unsigned int ctrla; /* 0x9C || 0xC4 */
152 unsigned int ctrlb; /* 0xA0 || 0xC8 */
153} sdrc_actim_t;
154
155typedef struct sdrc {
156 unsigned char res1[0x10];
157 unsigned int sysconfig; /* 0x10 */
158 unsigned int status; /* 0x14 */
159 unsigned char res2[0x28];
160 unsigned int cs_cfg; /* 0x40 */
161 unsigned int sharing; /* 0x44 */
162 unsigned char res3[0x18];
163 unsigned int dlla_ctrl; /* 0x60 */
164 unsigned int dlla_status; /* 0x64 */
165 unsigned int dllb_ctrl; /* 0x68 */
166 unsigned int dllb_status; /* 0x6C */
167 unsigned int power; /* 0x70 */
168 unsigned char res4[0xC];
169 sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */
170} sdrc_t;
171#endif /* __ASSEMBLY__ */
172
173#define DLLPHASE_90 (0x1 << 1)
174#define LOADDLL (0x1 << 2)
175#define ENADLL (0x1 << 3)
176#define DLL_DELAY_MASK 0xFF00
177#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
178
179#define PAGEPOLICY_HIGH (0x1 << 0)
180#define SRFRONRESET (0x1 << 7)
181#define WAKEUPPROC (0x1 << 26)
182
183#define DDR_SDRAM (0x1 << 0)
184#define DEEPPD (0x1 << 3)
185#define B32NOT16 (0x1 << 4)
186#define BANKALLOCATION (0x2 << 6)
187#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
188#define ADDRMUXLEGACY (0x1 << 19)
189#define CASWIDTH_10BITS (0x5 << 20)
190#define RASWIDTH_13BITS (0x2 << 24)
191#define BURSTLENGTH4 (0x2 << 0)
192#define CASL3 (0x3 << 4)
193#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
194#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
195#define ARE_ARCV_1 (0x1 << 0)
196#define ARCV (0x4e2 << 8) /* Autorefresh count */
197#define OMAP34XX_SDRC_CS0 0x80000000
198#define OMAP34XX_SDRC_CS1 0xA0000000
199#define CMD_NOP 0x0
200#define CMD_PRECHARGE 0x1
201#define CMD_AUTOREFRESH 0x2
202#define CMD_ENTR_PWRDOWN 0x3
203#define CMD_EXIT_PWRDOWN 0x4
204#define CMD_ENTR_SRFRSH 0x5
205#define CMD_CKE_HIGH 0x6
206#define CMD_CKE_LOW 0x7
207#define SOFTRESET (0x1 << 1)
208#define SMART_IDLE (0x2 << 3)
209#define REF_ON_IDLE (0x1 << 6)
210
211/* timer regs offsets (32 bit regs) */
212
213#ifndef __ASSEMBLY__
214typedef struct gptimer {
215 unsigned int tidr; /* 0x00 r */
216 unsigned char res[0xc];
217 unsigned int tiocp_cfg; /* 0x10 rw */
218 unsigned int tistat; /* 0x14 r */
219 unsigned int tisr; /* 0x18 rw */
220 unsigned int tier; /* 0x1c rw */
221 unsigned int twer; /* 0x20 rw */
222 unsigned int tclr; /* 0x24 rw */
223 unsigned int tcrr; /* 0x28 rw */
224 unsigned int tldr; /* 0x2c rw */
225 unsigned int ttgr; /* 0x30 rw */
226 unsigned int twpc; /* 0x34 r*/
227 unsigned int tmar; /* 0x38 rw*/
228 unsigned int tcar1; /* 0x3c r */
229 unsigned int tcicr; /* 0x40 rw */
230 unsigned int tcar2; /* 0x44 r */
231} gptimer_t;
232#endif /* __ASSEMBLY__ */
233
234/* enable sys_clk NO-prescale /1 */
235#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
236
237/* Watchdog */
238#ifndef __ASSEMBLY__
239typedef struct watchdog {
240 unsigned char res1[0x34];
241 unsigned int wwps; /* 0x34 r */
242 unsigned char res2[0x10];
243 unsigned int wspr; /* 0x48 rw */
244} watchdog_t;
245#endif /* __ASSEMBLY__ */
246
247#define WD_UNLOCK1 0xAAAA
248#define WD_UNLOCK2 0x5555
249
250/* PRCM */
251#define PRCM_BASE 0x48004000
252
253#ifndef __ASSEMBLY__
254typedef struct prcm {
255 unsigned int fclken_iva2; /* 0x00 */
256 unsigned int clken_pll_iva2; /* 0x04 */
257 unsigned char res1[0x1c];
258 unsigned int idlest_pll_iva2; /* 0x24 */
259 unsigned char res2[0x18];
260 unsigned int clksel1_pll_iva2 ; /* 0x40 */
261 unsigned int clksel2_pll_iva2; /* 0x44 */
262 unsigned char res3[0x8bc];
263 unsigned int clken_pll_mpu; /* 0x904 */
264 unsigned char res4[0x1c];
265 unsigned int idlest_pll_mpu; /* 0x924 */
266 unsigned char res5[0x18];
267 unsigned int clksel1_pll_mpu; /* 0x940 */
268 unsigned int clksel2_pll_mpu; /* 0x944 */
269 unsigned char res6[0xb8];
270 unsigned int fclken1_core; /* 0xa00 */
271 unsigned char res7[0xc];
272 unsigned int iclken1_core; /* 0xa10 */
273 unsigned int iclken2_core; /* 0xa14 */
274 unsigned char res8[0x28];
275 unsigned int clksel_core; /* 0xa40 */
276 unsigned char res9[0xbc];
277 unsigned int fclken_gfx; /* 0xb00 */
278 unsigned char res10[0xc];
279 unsigned int iclken_gfx; /* 0xb10 */
280 unsigned char res11[0x2c];
281 unsigned int clksel_gfx; /* 0xb40 */
282 unsigned char res12[0xbc];
283 unsigned int fclken_wkup; /* 0xc00 */
284 unsigned char res13[0xc];
285 unsigned int iclken_wkup; /* 0xc10 */
286 unsigned char res14[0xc];
287 unsigned int idlest_wkup; /* 0xc20 */
288 unsigned char res15[0x1c];
289 unsigned int clksel_wkup; /* 0xc40 */
290 unsigned char res16[0xbc];
291 unsigned int clken_pll; /* 0xd00 */
292 unsigned char res17[0x1c];
293 unsigned int idlest_ckgen; /* 0xd20 */
294 unsigned char res18[0x1c];
295 unsigned int clksel1_pll; /* 0xd40 */
296 unsigned int clksel2_pll; /* 0xd44 */
297 unsigned int clksel3_pll; /* 0xd48 */
298 unsigned char res19[0xb4];
299 unsigned int fclken_dss; /* 0xe00 */
300 unsigned char res20[0xc];
301 unsigned int iclken_dss; /* 0xe10 */
302 unsigned char res21[0x2c];
303 unsigned int clksel_dss; /* 0xe40 */
304 unsigned char res22[0xbc];
305 unsigned int fclken_cam; /* 0xf00 */
306 unsigned char res23[0xc];
307 unsigned int iclken_cam; /* 0xf10 */
308 unsigned char res24[0x2c];
309 unsigned int clksel_cam; /* 0xf40 */
310 unsigned char res25[0xbc];
311 unsigned int fclken_per; /* 0x1000 */
312 unsigned char res26[0xc];
313 unsigned int iclken_per; /* 0x1010 */
314 unsigned char res27[0x2c];
315 unsigned int clksel_per; /* 0x1040 */
316 unsigned char res28[0xfc];
317 unsigned int clksel1_emu; /* 0x1140 */
318} prcm_t;
319#else /* __ASSEMBLY__ */
320#define CM_CLKSEL_CORE 0x48004a40
321#define CM_CLKSEL_GFX 0x48004b40
322#define CM_CLKSEL_WKUP 0x48004c40
323#define CM_CLKEN_PLL 0x48004d00
324#define CM_CLKSEL1_PLL 0x48004d40
325#define CM_CLKSEL1_EMU 0x48005140
326#endif /* __ASSEMBLY__ */
327
328#define PRM_BASE 0x48306000
329
330#ifndef __ASSEMBLY__
331typedef struct prm {
332 unsigned char res1[0xd40];
333 unsigned int clksel; /* 0xd40 */
334 unsigned char res2[0x50c];
335 unsigned int rstctrl; /* 0x1250 */
336 unsigned char res3[0x1c];
337 unsigned int clksrc_ctrl; /* 0x1270 */
338} prm_t;
339#else /* __ASSEMBLY__ */
340#define PRM_RSTCTRL 0x48307250
341#endif /* __ASSEMBLY__ */
342
343#define SYSCLKDIV_1 (0x1 << 6)
344#define SYSCLKDIV_2 (0x1 << 7)
345
346#define CLKSEL_GPT1 (0x1 << 0)
347
348#define EN_GPT1 (0x1 << 0)
349#define EN_32KSYNC (0x1 << 2)
350
351#define ST_WDT2 (0x1 << 5)
352
353#define ST_MPU_CLK (0x1 << 0)
354
355#define ST_CORE_CLK (0x1 << 0)
356
357#define ST_PERIPH_CLK (0x1 << 1)
358
359#define ST_IVA2_CLK (0x1 << 0)
360
361#define RESETDONE (0x1 << 0)
362
363#define TCLR_ST (0x1 << 0)
364#define TCLR_AR (0x1 << 1)
365#define TCLR_PRE (0x1 << 5)
366
367/* SMX-APE */
368#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
369#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
370#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
371#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
372
373#ifndef __ASSEMBLY__
374typedef struct pm {
375 unsigned char res1[0x48];
376 unsigned int req_info_permission_0; /* 0x48 */
377 unsigned char res2[0x4];
378 unsigned int read_permission_0; /* 0x50 */
379 unsigned char res3[0x4];
380 unsigned int wirte_permission_0; /* 0x58 */
381 unsigned char res4[0x4];
382 unsigned int addr_match_1; /* 0x58 */
383 unsigned char res5[0x4];
384 unsigned int req_info_permission_1; /* 0x68 */
385 unsigned char res6[0x14];
386 unsigned int addr_match_2; /* 0x80 */
387} pm_t;
388#endif /*__ASSEMBLY__ */
389
390/* Permission values for registers -Full fledged permissions to all */
391#define UNLOCK_1 0xFFFFFFFF
392#define UNLOCK_2 0x00000000
393#define UNLOCK_3 0x0000FFFF
394
395#define NOT_EARLY 0
396
397/* I2C base */
398#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
399#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
400#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
401
402#endif /* _CPU_H */