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Vladimir Zapolskiy52f69f82012-04-19 04:33:08 +00001/*
2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Vladimir Zapolskiy52f69f82012-04-19 04:33:08 +00005 */
6
7#ifndef _LPC32XX_TIMER_H
8#define _LPC32XX_TIMER_H
9
10#include <asm/types.h>
11
12/* Timer/Counter Registers */
13struct timer_regs {
14 u32 ir; /* Interrupt Register */
15 u32 tcr; /* Timer Control Register */
16 u32 tc; /* Timer Counter */
17 u32 pr; /* Prescale Register */
18 u32 pc; /* Prescale Counter */
19 u32 mcr; /* Match Control Register */
20 u32 mr[4]; /* Match Registers */
21 u32 ccr; /* Capture Control Register */
22 u32 cr[4]; /* Capture Registers */
23 u32 emr; /* External Match Register */
24 u32 reserved[12];
25 u32 ctcr; /* Count Control Register */
26};
27
28/* Timer/Counter Interrupt Register bits */
29#define TIMER_IR_CR(n) (1 << ((n) + 4))
30#define TIMER_IR_MR(n) (1 << (n))
31
32/* Timer/Counter Timer Control Register bits */
33#define TIMER_TCR_COUNTER_RESET (1 << 1)
34#define TIMER_TCR_COUNTER_ENABLE (1 << 0)
35#define TIMER_TCR_COUNTER_DISABLE (0 << 0)
36
37/* Timer/Counter Match Control Register bits */
38#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2))
39#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1))
40#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n)))
41
42/* Timer/Counter Capture Control Register bits */
43#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2))
44#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1))
45#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n)))
46
47/* Timer/Counter External Match Register bits */
48#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4))
49#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4))
50#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4))
51#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4))
52#define TIMER_EMR_EM(n) (1 << (n))
53
54/* Timer/Counter Count Control Register bits */
55#define TIMER_CTCR_INPUT(n) ((n) << 2)
56#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0)
57#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0)
58#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0)
59#define TIMER_CTCR_MODE_TIMER (0x0 << 0)
60
61#endif /* _LPC32XX_TIMER_H */