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gerrit.cesnet.cz / github / trini / u-boot / 0a85a9e70593a9cd90fbbbdaad8443e31a9dd5a3 / . / arch / m68k / include / asm / m520x.h
blob: 71f147e751fa77ace9b5d494c36630e882953a0d [file] [log] [blame]
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]1/*
2 * m520x.h -- Definitions for Freescale Coldfire 520x
3 *
4 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __M520X__
27#define __M520X__
28
29/* *** System Control Module (SCM) *** */
30#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
31#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
32#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
33#define MPROT_MTR 4
34#define MPROT_MTW 2
35#define MPROT_MPL 1
36
37#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
38#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
39#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
40
41#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
42
43#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
44#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
45#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
46#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
47#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
48#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
49
50#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
51#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
52#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
53#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
54#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
55#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
56#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
57
58#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
59#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
60#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
61#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
62#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
63
64#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
65#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
66#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
67
68#define PACR_SP 4
69#define PACR_WP 2
70#define PACR_TP 1
71
72#define SCM_BMT_BME (0x00000008)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]73#define SCM_BMT_BMT(x) ((x) & 0x07)
74#define SCM_BMT_BMT1024 (0x0000)
75#define SCM_BMT_BMT512 (0x0001)
76#define SCM_BMT_BMT256 (0x0002)
77#define SCM_BMT_BMT128 (0x0003)
78#define SCM_BMT_BMT64 (0x0004)
79#define SCM_BMT_BMT32 (0x0005)
80#define SCM_BMT_BMT16 (0x0006)
81#define SCM_BMT_BMT8 (0x0007)
82
83#define SCM_CWCR_RO (0x8000)
84#define SCM_CWCR_CWR_WH (0x0100)
85#define SCM_CWCR_CWE (0x0080)
86#define SCM_CWRI_WINDOW (0x0060)
87#define SCM_CWRI_RESET (0x0040)
88#define SCM_CWRI_INT_RESET (0x0020)
89#define SCM_CWRI_INT (0x0000)
90#define SCM_CWCR_CWT(x) (((x) & 0x001F))
91
92#define SCM_ISR_CFEI (0x02)
93#define SCM_ISR_CWIC (0x01)
94
95#define SCM_CFIER_ECFEI (0x01)
96
97#define SCM_CFLOC_LOC (0x80)
98
99#define SCM_CFATR_WRITE (0x80)
100#define SCM_CFATR_SZ32 (0x20)
101#define SCM_CFATR_SZ16 (0x10)
102#define SCM_CFATR_SZ08 (0x00)
103#define SCM_CFATR_CACHE (0x08)
104#define SCM_CFATR_MODE (0x02)
105#define SCM_CFATR_TYPE (0x01)
106
107/* *** Interrupt Controller (INTC) *** */
108#define INT0_LO_RSVD0 (0)
109#define INT0_LO_EPORT_F1 (1)
110#define INT0_LO_EPORT_F4 (2)
111#define INT0_LO_EPORT_F7 (3)
112#define INT1_LO_PIT0 (4)
113#define INT1_LO_PIT1 (5)
114/* 6 - 7 rsvd */
115#define INT0_LO_EDMA_00 (8)
116#define INT0_LO_EDMA_01 (9)
117#define INT0_LO_EDMA_02 (10)
118#define INT0_LO_EDMA_03 (11)
119#define INT0_LO_EDMA_04 (12)
120#define INT0_LO_EDMA_05 (13)
121#define INT0_LO_EDMA_06 (14)
122#define INT0_LO_EDMA_07 (15)
123#define INT0_LO_EDMA_08 (16)
124#define INT0_LO_EDMA_09 (17)
125#define INT0_LO_EDMA_10 (18)
126#define INT0_LO_EDMA_11 (19)
127#define INT0_LO_EDMA_12 (20)
128#define INT0_LO_EDMA_13 (21)
129#define INT0_LO_EDMA_14 (22)
130#define INT0_LO_EDMA_15 (23)
131#define INT0_LO_EDMA_ERR (24)
132#define INT0_LO_SCM_CWIC (25)
133#define INT0_LO_UART0 (26)
134#define INT0_LO_UART1 (27)
135#define INT0_LO_UART2 (28)
136/* 29 rsvd */
137#define INT0_LO_I2C (30)
138#define INT0_LO_QSPI (31)
139
140#define INT0_HI_DTMR0 (32)
141#define INT0_HI_DTMR1 (33)
142#define INT0_HI_DTMR2 (34)
143#define INT0_HI_DTMR3 (35)
144#define INT0_HI_FEC0_TXF (36)
145#define INT0_HI_FEC0_TXB (37)
146#define INT0_HI_FEC0_UN (38)
147#define INT0_HI_FEC0_RL (39)
148#define INT0_HI_FEC0_RXF (40)
149#define INT0_HI_FEC0_RXB (41)
150#define INT0_HI_FEC0_MII (42)
151#define INT0_HI_FEC0_LC (43)
152#define INT0_HI_FEC0_HBERR (44)
153#define INT0_HI_FEC0_GRA (45)
154#define INT0_HI_FEC0_EBERR (46)
155#define INT0_HI_FEC0_BABT (47)
156#define INT0_HI_FEC0_BABR (48)
157/* 49 - 61 rsvd */
158#define INT0_HI_SCMISR_CFEI (62)
159
160/* *** Reset Controller Module (RCM) *** */
161#define RCM_RCR_SOFTRST (0x80)
162#define RCM_RCR_FRCRSTOUT (0x40)
163
164#define RCM_RSR_SOFT (0x20)
165#define RCM_RSR_WDOG (0x10)
166#define RCM_RSR_POR (0x08)
167#define RCM_RSR_EXT (0x04)
168#define RCM_RSR_WDR_CORE (0x02)
169#define RCM_RSR_LOL (0x01)
170
171/* *** Chip Configuration Module (CCM) *** */
172#define CCM_CCR_CSC (0x0200)
173#define CCM_CCR_OSCFREQ (0x0080)
174#define CCM_CCR_LIMP (0x0040)
175#define CCM_CCR_LOAD (0x0020)
176#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3)
177#define CCM_CCR_OSC_MODE (0x0004)
178#define CCM_CCR_PLL_MODE (0x0002)
179#define CCM_CCR_RESERVED (0x0001)
180
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]181#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]182#define CCM_CIR_PRN(x) ((x) & 0x003F)
183
184/* *** General Purpose I/O (GPIO) *** */
185#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F)
186#define GPIO_PDR_BE(x) ((x) & 0x0F)
187#define GPIO_PDR_CS(x) (((x) & 0x07) << 1)
188#define GPIO_PDR_FECI2C(x) ((x) & 0x0F)
189#define GPIO_PDR_QSPI(x) ((x) & 0x0F)
190#define GPIO_PDR_TIMER(x) ((x) & 0x0F)
191#define GPIO_PDR_UART(x) ((x) & 0xFF)
192#define GPIO_PDR_FECH(x) ((x) & 0xFF)
193#define GPIO_PDR_FECL(x) ((x) & 0xFF)
194
195#define GPIO_PAR_FBCTL_OE (0x10)
196#define GPIO_PAR_FBCTL_TA (0x08)
197#define GPIO_PAR_FBCTL_RWB (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]198#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]199#define GPIO_PAR_FBCTL_TS_TS (0x03)
200#define GPIO_PAR_FBCTL_TS_DMA (0x02)
201
202#define GPIO_PAR_BE3 (0x08)
203#define GPIO_PAR_BE2 (0x04)
204#define GPIO_PAR_BE1 (0x02)
205#define GPIO_PAR_BE0 (0x01)
206
207#define GPIO_PAR_CS3 (0x08)
208#define GPIO_PAR_CS2 (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]209#define GPIO_PAR_CS1_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]210#define GPIO_PAR_CS1_CS1 (0x03)
211#define GPIO_PAR_CS1_SDCS1 (0x02)
212
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]213#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F)
214#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]215#define GPIO_PAR_FECI2C_MDC_MDC (0xC0)
216#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
217#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]218#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]219#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30)
220#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
221#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]222#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0)
223#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]224#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
225#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]226#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]227#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
228#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01)
229
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]230#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]231#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0)
232#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80)
233#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]234#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]235#define GPIO_PAR_QSPI_DIN_DIN (0x30)
236#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20)
237#define GPIO_PAR_QSPI_DIN_U2CTS (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]238#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]239#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C)
240#define GPIO_PAR_QSPI_DOUT_SDA (0x08)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]241#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]242#define GPIO_PAR_QSPI_SCK_SCK (0x03)
243#define GPIO_PAR_QSPI_SCK_SCL (0x02)
244
245#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6)
246#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4)
247#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2)
248#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]249#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]250#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0)
251#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80)
252#define GPIO_PAR_TMR_TIN3_U2CTS (0x40)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]253#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]254#define GPIO_PAR_TMR_TIN2_TIN2 (0x30)
255#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20)
256#define GPIO_PAR_TMR_TIN2_U2RTS (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]257#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]258#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C)
259#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08)
260#define GPIO_PAR_TMR_TIN1_U2RXD (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]261#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]262#define GPIO_PAR_TMR_TIN0_TIN0 (0x03)
263#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02)
264#define GPIO_PAR_TMR_TIN0_U2TXD (0x01)
265
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]266#define GPIO_PAR_UART1_UNMASK (0xF03F)
267#define GPIO_PAR_UART0_UNMASK (0xFFC0)
268#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]269#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00)
270#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800)
271#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]272#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]273#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300)
274#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200)
275#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100)
276#define GPIO_PAR_UART_U1TXD (0x0080)
277#define GPIO_PAR_UART_U1RXD (0x0040)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]278#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]279#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030)
280#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020)
281#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]282#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]283#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C)
284#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008)
285#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004)
286#define GPIO_PAR_UART_U0TXD (0x0002)
287#define GPIO_PAR_UART_U0RXD (0x0001)
288
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]289#define GPIO_PAR_FEC_7W_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]290#define GPIO_PAR_FEC_7W_FEC (0x0C)
291#define GPIO_PAR_FEC_7W_U1RTS (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]292#define GPIO_PAR_FEC_MII_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]293#define GPIO_PAR_FEC_MII_FEC (0x03)
294#define GPIO_PAR_FEC_MII_UnCTS (0x01)
295
296#define GPIO_PAR_IRQ_IRQ4 (0x01)
297
298#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6)
299#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4)
300#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2)
301#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]302#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F)
303#define GPIO_MSCR_FB_DUP_UNMASK (0xCF)
304#define GPIO_MSCR_FB_DLO_UNMASK (0xF3)
305#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]306
307#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4)
308#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2)
309#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]310#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF)
311#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3)
312#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]313
314#define MSCR_25VDDR (0x03)
315#define MSCR_18VDDR_FULL (0x02)
316#define MSCR_OPENDRAIN (0x01)
317#define MSCR_18VDDR_HALF (0x00)
318
319#define GPIO_DSCR_I2C(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]320#define GPIO_DSCR_I2C_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]321
322#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]323#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]324#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]325#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]326#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]327#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]328
329#define GPIO_DSCR_FEC(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]330#define GPIO_DSCR_FEC_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]331
332#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]333#define GPIO_DSCR_UART_UART1_UNMASK (0xCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]334#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]335#define GPIO_DSCR_UART_UART0_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]336#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]337#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]338
339#define GPIO_DSCR_QSPI(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]340#define GPIO_DSCR_QSPI_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]341
342#define DSCR_50PF (0x03)
343#define DSCR_30PF (0x02)
344#define DSCR_20PF (0x01)
345#define DSCR_10PF (0x00)
346
347/* *** Phase Locked Loop (PLL) *** */
348#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]349#define PLL_PODR_CPUDIV_UNMASK (0x0F)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]350#define PLL_PODR_BUSDIV(x) ((x) & 0x0F)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]351#define PLL_PODR_BUSDIV_UNMASK (0xF0)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]352
353#define PLL_PCR_DITHEN (0x80)
354#define PLL_PCR_DITHDEV(x) ((x) & 0x07)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]355#define PLL_PCR_DITHDEV_UNMASK (0xF8)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]356
357#endif /* __M520X__ */