| Wolfgang Denk | 70a2047 | 2005-09-25 15:59:01 +0200 | [diff] [blame] | 1 | gafr0_l: 0x80001005 |
| 2 | gafr0_u: 0xa5128012 |
| 3 | gafr1_l: 0x699a9558 |
| 4 | gafr1_u: 0xaaa5aa6a |
| 5 | gafr2_l: 0xaaaaaaaa |
| 6 | gafr2_u: 0x2 |
| 7 | gpcr0: 0x1800400 |
| 8 | gpcr1: 0x0 |
| 9 | gpcr2: 0x0 |
| 10 | gpdr0: 0xc1818440 |
| 11 | gpdr1: 0xfcffab82 |
| 12 | gpdr2: 0x1ffff |
| 13 | gpsr0: 0x8000 |
| 14 | gpsr1: 0x3f0002 |
| 15 | gpsr2: 0x1c000 |
| 16 | |
| 17 | |
| 18 | #define CFG_GAFR0_L_VAL 0x80001005 |
| 19 | #define CFG_GAFR0_U_VAL 0xa5128012 |
| 20 | #define CFG_GAFR1_L_VAL 0x699a9558 |
| 21 | #define CFG_GAFR1_U_VAL 0xaaa5aa6a |
| 22 | #define CFG_GAFR2_L_VAL 0xaaaaaaaa |
| 23 | #define CFG_GAFR2_U_VAL 0x2 |
| 24 | #define CFG_GPCR0_VAL 0x1800400 |
| 25 | #define CFG_GPCR1_VAL 0x0 |
| 26 | #define CFG_GPCR2_VAL 0x0 |
| 27 | #define CFG_GPDR0_VAL 0xc1818440 |
| 28 | #define CFG_GPDR1_VAL 0xfcffab82 |
| 29 | #define CFG_GPDR2_VAL 0x1ffff |
| 30 | #define CFG_GPSR0_VAL 0x8000 |
| 31 | #define CFG_GPSR1_VAL 0x3f0002 |
| 32 | #define CFG_GPSR2_VAL 0x1c000 |
| 33 | |
| 34 | |
| 35 | GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET# |
| 36 | GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET# |
| 37 | GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA |
| 38 | GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ# |
| 39 | GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH |
| 40 | GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH# |
| 41 | GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK |
| 42 | GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD# |
| 43 | GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD# |
| 44 | GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD# |
| 45 | GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED |
| 46 | GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK |
| 47 | GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK |
| 48 | GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT |
| 49 | GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ |
| 50 | GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1# |
| 51 | GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0 |
| 52 | GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB |
| 53 | GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY |
| 54 | GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O# |
| 55 | GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0 |
| 56 | GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI |
| 57 | GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O# |
| 58 | GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK |
| 59 | GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM |
| 60 | GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD |
| 61 | GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD |
| 62 | GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK |
| 63 | GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK |
| 64 | GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0 |
| 65 | GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT |
| 66 | GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC |
| 67 | GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1 |
| 68 | GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5# |
| 69 | GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD |
| 70 | GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS |
| 71 | GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD |
| 72 | GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR |
| 73 | GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI |
| 74 | GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD |
| 75 | GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR |
| 76 | GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS |
| 77 | GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD |
| 78 | GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD |
| 79 | GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS |
| 80 | GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS |
| 81 | GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD |
| 82 | GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD |
| 83 | GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE# |
| 84 | GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE# |
| 85 | GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR# |
| 86 | GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW# |
| 87 | GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1# |
| 88 | GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2# |
| 89 | GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL |
| 90 | GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG# |
| 91 | GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT# |
| 92 | GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16# |
| 93 | GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0 |
| 94 | GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1 |
| 95 | GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2 |
| 96 | GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3 |
| 97 | GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4 |
| 98 | GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5 |
| 99 | GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6 |
| 100 | GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7 |
| 101 | GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8 |
| 102 | GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9 |
| 103 | GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10 |
| 104 | GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11 |
| 105 | GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12 |
| 106 | GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13 |
| 107 | GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14 |
| 108 | GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15 |
| 109 | GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK |
| 110 | GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK |
| 111 | GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK |
| 112 | GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS |
| 113 | GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2# |
| 114 | GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3# |
| 115 | GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4# |
| 116 | GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc= |
| 117 | GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc= |
| 118 | GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc= |
| 119 | GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc= |