blob: ff1b892b51da2283b532993f29612f8fef4fd91a [file] [log] [blame]
Jon Loeliger3dd2db52007-10-16 13:54:01 -05001/*
2 * Copyright 2007 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
Jon Loeligerc9974ab2008-01-04 11:58:23 -060022
Jon Loeliger3dd2db52007-10-16 13:54:01 -050023#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/immap_86xx.h>
28#include <asm/immap_fsl_pci.h>
Jon Loeligerc9974ab2008-01-04 11:58:23 -060029#include <i2c.h>
Jon Loeliger3dd2db52007-10-16 13:54:01 -050030#include <asm/io.h>
Jon Loeliger1df170f2008-01-04 12:07:27 -060031#include <libfdt.h>
32#include <fdt_support.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060033#include <spd_sdram.h>
Jon Loeliger3dd2db52007-10-16 13:54:01 -050034
35#include "../common/pixis.h"
36
37#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
38extern void ddr_enable_ecc(unsigned int dram_size);
39#endif
40
Jon Loeliger3dd2db52007-10-16 13:54:01 -050041void sdram_init(void);
42long int fixed_sdram(void);
Jon Loeligerc9974ab2008-01-04 11:58:23 -060043void mpc8610hpcd_diu_init(void);
44
Jon Loeliger3dd2db52007-10-16 13:54:01 -050045
46/* called before any console output */
47int board_early_init_f(void)
48{
49 volatile immap_t *immap = (immap_t *)CFG_IMMR;
50 volatile ccsr_gur_t *gur = &immap->im_gur;
51
York Suna8778802007-10-29 13:58:39 -050052 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
53
54 return 0;
55}
56
57int misc_init_r(void)
58{
59 u8 tmp_val, version;
60
61 /*Do not use 8259PIC*/
62 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
63 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
64
65 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
66 version = in8(PIXIS_BASE + PIXIS_PVER);
67 if(version >= 0x07) {
68 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
69 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
70 }
71
72 /* Using this for DIU init before the driver in linux takes over
73 * Enable the TFP410 Encoder (I2C address 0x38)
74 */
75
76 tmp_val = 0xBF;
77 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
78 /* Verify if enabled */
79 tmp_val = 0;
80 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
81 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
82
83 tmp_val = 0x10;
84 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
85 /* Verify if enabled */
86 tmp_val = 0;
87 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
88 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
89
90#ifdef CONFIG_FSL_DIU_FB
91 mpc8610hpcd_diu_init();
92#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -050093
94 return 0;
95}
96
97int checkboard(void)
98{
99 volatile immap_t *immap = (immap_t *)CFG_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500100 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
101
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200102 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
103 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
Kumar Galaa036b042008-06-19 01:45:50 -0500104 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
105 in8(PIXIS_BASE + PIXIS_PVER));
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500106
107 mcm->abcr |= 0x00010000; /* 0 */
108 mcm->hpmr3 = 0x80000008; /* 4c */
109 mcm->hpmr0 = 0;
110 mcm->hpmr1 = 0;
111 mcm->hpmr2 = 0;
112 mcm->hpmr4 = 0;
113 mcm->hpmr5 = 0;
114
115 return 0;
116}
117
118
Becky Bruce9973e3c2008-06-09 16:03:40 -0500119phys_size_t
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500120initdram(int board_type)
121{
122 long dram_size = 0;
123
124#if defined(CONFIG_SPD_EEPROM)
125 dram_size = spd_sdram();
126#else
127 dram_size = fixed_sdram();
128#endif
129
130#if defined(CFG_RAMBOOT)
131 puts(" DDR: ");
132 return dram_size;
133#endif
134
135#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
136 /*
137 * Initialize and enable DDR ECC.
138 */
139 ddr_enable_ecc(dram_size);
140#endif
141
142 puts(" DDR: ");
143 return dram_size;
144}
145
146
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500147#if !defined(CONFIG_SPD_EEPROM)
148/*
149 * Fixed sdram init -- doesn't use serial presence detect.
150 */
151
152long int fixed_sdram(void)
153{
154#if !defined(CFG_RAMBOOT)
155 volatile immap_t *immap = (immap_t *)CFG_IMMR;
156 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
157 uint d_init;
158
159 ddr->cs0_bnds = 0x0000001f;
160 ddr->cs0_config = 0x80010202;
161
Kumar Gala45239cf2008-04-29 10:27:08 -0500162 ddr->timing_cfg_3 = 0x00000000;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500163 ddr->timing_cfg_0 = 0x00260802;
164 ddr->timing_cfg_1 = 0x3935d322;
165 ddr->timing_cfg_2 = 0x14904cc8;
166 ddr->sdram_mode_1 = 0x00480432;
167 ddr->sdram_mode_2 = 0x00000000;
168 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
169 ddr->sdram_data_init = 0xDEADBEEF;
170 ddr->sdram_clk_cntl = 0x03800000;
171 ddr->sdram_cfg_2 = 0x04400010;
172
173#if defined(CONFIG_DDR_ECC)
174 ddr->err_int_en = 0x0000000d;
175 ddr->err_disable = 0x00000000;
176 ddr->err_sbe = 0x00010000;
177#endif
178 asm("sync;isync");
179
180 udelay(500);
181
182 ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
183
184
185#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
186 d_init = 1;
187 debug("DDR - 1st controller: memory initializing\n");
188 /*
189 * Poll until memory is initialized.
190 * 512 Meg at 400 might hit this 200 times or so.
191 */
192 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
193 udelay(1000);
194
195 debug("DDR: memory initialized\n\n");
196 asm("sync; isync");
197 udelay(500);
198#endif
199
200 return 512 * 1024 * 1024;
201#endif
202 return CFG_SDRAM_SIZE * 1024 * 1024;
203}
204
205#endif
206
207#if defined(CONFIG_PCI)
208/*
209 * Initialize PCI Devices, report devices found.
210 */
211
212#ifndef CONFIG_PCI_PNP
213static struct pci_config_table pci_fsl86xxads_config_table[] = {
214 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
215 PCI_IDSEL_NUMBER, PCI_ANY_ID,
216 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
217 PCI_ENET0_MEMADDR,
218 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
219 {}
220};
221#endif
222
223
224static struct pci_controller pci1_hose = {
225#ifndef CONFIG_PCI_PNP
226config_table:pci_mpc86xxcts_config_table
227#endif
228};
229#endif /* CONFIG_PCI */
230
231#ifdef CONFIG_PCIE1
232static struct pci_controller pcie1_hose;
233#endif
234
235#ifdef CONFIG_PCIE2
236static struct pci_controller pcie2_hose;
237#endif
238
239int first_free_busno = 0;
240
241void pci_init_board(void)
242{
243 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
244 volatile ccsr_gur_t *gur = &immap->im_gur;
245 uint devdisr = gur->devdisr;
Jon Loeligera551cee2008-02-20 14:22:26 -0600246 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
247 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
248 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
249 >> MPC8610_PORBMSR_HA_SHIFT;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500250
251 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
252 devdisr, io_sel, host_agent);
253
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500254#ifdef CONFIG_PCIE1
255 {
256 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
257 extern void fsl_pci_init(struct pci_controller *hose);
258 struct pci_controller *hose = &pcie1_hose;
259 int pcie_configured = (io_sel == 1) || (io_sel == 4);
260 int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
261 (host_agent == 5);
262
263 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
264 printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
265 pcie_ep ? "End Point" : "Root Complex",
266 (uint)pci);
267 if (pci->pme_msg_det)
268 pci->pme_msg_det = 0xffffffff;
269
270 /* inbound */
271 pci_set_region(hose->regions + 0,
272 CFG_PCI_MEMORY_BUS,
273 CFG_PCI_MEMORY_PHYS,
274 CFG_PCI_MEMORY_SIZE,
275 PCI_REGION_MEM | PCI_REGION_MEMORY);
276
277 /* outbound memory */
278 pci_set_region(hose->regions + 1,
279 CFG_PCIE1_MEM_BASE,
280 CFG_PCIE1_MEM_PHYS,
281 CFG_PCIE1_MEM_SIZE,
282 PCI_REGION_MEM);
283
284 /* outbound io */
285 pci_set_region(hose->regions + 2,
286 CFG_PCIE1_IO_BASE,
287 CFG_PCIE1_IO_PHYS,
288 CFG_PCIE1_IO_SIZE,
289 PCI_REGION_IO);
290
291 hose->region_count = 3;
292
293 hose->first_busno = first_free_busno;
294 pci_setup_indirect(hose, (int)&pci->cfg_addr,
295 (int)&pci->cfg_data);
296
297 fsl_pci_init(hose);
298
299 first_free_busno = hose->last_busno + 1;
300 printf(" PCI-Express 1 on bus %02x - %02x\n",
301 hose->first_busno, hose->last_busno);
302
303 } else
304 puts(" PCI-Express 1: Disabled\n");
305 }
306#else
307 puts("PCI-Express 1: Disabled\n");
308#endif /* CONFIG_PCIE1 */
309
310
311#ifdef CONFIG_PCIE2
312 {
313 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
314 extern void fsl_pci_init(struct pci_controller *hose);
315 struct pci_controller *hose = &pcie2_hose;
316
317 int pcie_configured = (io_sel == 0) || (io_sel == 4);
318 int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
319 (host_agent == 4);
320
321 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
322 printf(" PCI-Express 2 connected to slot as %s" \
323 " (base address %x)\n",
324 pcie_ep ? "End Point" : "Root Complex",
325 (uint)pci);
326 if (pci->pme_msg_det)
327 pci->pme_msg_det = 0xffffffff;
328
329 /* inbound */
330 pci_set_region(hose->regions + 0,
331 CFG_PCI_MEMORY_BUS,
332 CFG_PCI_MEMORY_PHYS,
333 CFG_PCI_MEMORY_SIZE,
334 PCI_REGION_MEM | PCI_REGION_MEMORY);
335
336 /* outbound memory */
337 pci_set_region(hose->regions + 1,
338 CFG_PCIE2_MEM_BASE,
339 CFG_PCIE2_MEM_PHYS,
340 CFG_PCIE2_MEM_SIZE,
341 PCI_REGION_MEM);
342
343 /* outbound io */
344 pci_set_region(hose->regions + 2,
345 CFG_PCIE2_IO_BASE,
346 CFG_PCIE2_IO_PHYS,
347 CFG_PCIE2_IO_SIZE,
348 PCI_REGION_IO);
349
350 hose->region_count = 3;
351
352 hose->first_busno = first_free_busno;
353 pci_setup_indirect(hose, (int)&pci->cfg_addr,
354 (int)&pci->cfg_data);
355
356 fsl_pci_init(hose);
357
358 first_free_busno = hose->last_busno + 1;
359 printf(" PCI-Express 2 on bus %02x - %02x\n",
360 hose->first_busno, hose->last_busno);
361 } else
362 puts(" PCI-Express 2: Disabled\n");
363 }
364#else
365 puts("PCI-Express 2: Disabled\n");
366#endif /* CONFIG_PCIE2 */
367
368
369#ifdef CONFIG_PCI1
370 {
371 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
372 extern void fsl_pci_init(struct pci_controller *hose);
373 struct pci_controller *hose = &pci1_hose;
374 int pci_agent = (host_agent >= 4) && (host_agent <= 6);
375
376 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
377 printf(" PCI connected to PCI slots as %s" \
378 " (base address %x)\n",
379 pci_agent ? "Agent" : "Host",
380 (uint)pci);
381
382 /* inbound */
383 pci_set_region(hose->regions + 0,
384 CFG_PCI_MEMORY_BUS,
385 CFG_PCI_MEMORY_PHYS,
386 CFG_PCI_MEMORY_SIZE,
387 PCI_REGION_MEM | PCI_REGION_MEMORY);
388
389 /* outbound memory */
390 pci_set_region(hose->regions + 1,
391 CFG_PCI1_MEM_BASE,
392 CFG_PCI1_MEM_PHYS,
393 CFG_PCI1_MEM_SIZE,
394 PCI_REGION_MEM);
395
396 /* outbound io */
397 pci_set_region(hose->regions + 2,
398 CFG_PCI1_IO_BASE,
399 CFG_PCI1_IO_PHYS,
400 CFG_PCI1_IO_SIZE,
401 PCI_REGION_IO);
402
403 hose->region_count = 3;
404
405 hose->first_busno = first_free_busno;
406 pci_setup_indirect(hose, (int) &pci->cfg_addr,
407 (int) &pci->cfg_data);
408
409 fsl_pci_init(hose);
410
411 first_free_busno = hose->last_busno + 1;
412 printf(" PCI on bus %02x - %02x\n",
413 hose->first_busno, hose->last_busno);
414
415
416 } else
417 puts(" PCI: Disabled\n");
418 }
419#endif /* CONFIG_PCI1 */
420}
421
Jon Loeliger1df170f2008-01-04 12:07:27 -0600422#if defined(CONFIG_OF_BOARD_SETUP)
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500423void
424ft_board_setup(void *blob, bd_t *bd)
425{
Jon Loeliger1df170f2008-01-04 12:07:27 -0600426 int node, tmp[2];
427 const char *path;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500428
Jon Loeliger1df170f2008-01-04 12:07:27 -0600429 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
430 "timebase-frequency", bd->bi_busfreq / 4, 1);
431 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
432 "bus-frequency", bd->bi_busfreq, 1);
433 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
434 "clock-frequency", bd->bi_intfreq, 1);
435 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
436 "bus-frequency", bd->bi_busfreq, 1);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500437
Jon Loeliger1df170f2008-01-04 12:07:27 -0600438 do_fixup_by_compat_u32(blob, "ns16550",
439 "clock-frequency", bd->bi_busfreq, 1);
440
441 fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
442
443
444 node = fdt_path_offset(blob, "/aliases");
445 tmp[0] = 0;
446 if (node >= 0) {
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500447
448#ifdef CONFIG_PCI1
Jon Loeliger1df170f2008-01-04 12:07:27 -0600449 path = fdt_getprop(blob, node, "pci0", NULL);
450 if (path) {
451 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
452 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
453 }
454
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500455#endif
456#ifdef CONFIG_PCIE1
Jon Loeliger1df170f2008-01-04 12:07:27 -0600457 path = fdt_getprop(blob, node, "pci1", NULL);
458 if (path) {
459 tmp[1] = pcie1_hose.last_busno
460 - pcie1_hose.first_busno;
461 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500462 }
463#endif
464#ifdef CONFIG_PCIE2
Jon Loeliger1df170f2008-01-04 12:07:27 -0600465 path = fdt_getprop(blob, node, "pci2", NULL);
466 if (path) {
467 tmp[1] = pcie2_hose.last_busno
468 - pcie2_hose.first_busno;
469 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
470 }
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500471#endif
Jon Loeliger1df170f2008-01-04 12:07:27 -0600472 }
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500473}
474#endif
475
476/*
477 * get_board_sys_clk
478 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
479 */
480
481unsigned long
482get_board_sys_clk(ulong dummy)
483{
York Suna8778802007-10-29 13:58:39 -0500484 u8 i;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500485 ulong val = 0;
486 ulong a;
487
488 a = PIXIS_BASE + PIXIS_SPD;
489 i = in8(a);
490 i &= 0x07;
491
492 switch (i) {
493 case 0:
494 val = 33333000;
495 break;
496 case 1:
497 val = 39999600;
498 break;
499 case 2:
500 val = 49999500;
501 break;
502 case 3:
503 val = 66666000;
504 break;
505 case 4:
506 val = 83332500;
507 break;
508 case 5:
509 val = 99999000;
510 break;
511 case 6:
512 val = 133332000;
513 break;
514 case 7:
515 val = 166665000;
516 break;
517 }
518
519 return val;
520}