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wdenk8ed96042005-01-09 23:16:25 +00001/*
2 * (C) Copyright 2004
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
6 *
7 * Configuration settings for the 242x TI H4 board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 */
34#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
35#define CONFIG_OMAP 1 /* in a TI OMAP core */
36#define CONFIG_OMAP2420 1 /* which is in a 2420 */
37#define CONFIG_OMAP2420H4 1 /* and on a H4 board */
wdenk082acfd2005-01-10 00:01:04 +000038/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */
39/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
wdenk8ed96042005-01-09 23:16:25 +000040
wdenk289f9322005-01-12 00:15:14 +000041/* Clock config to target*/
42#define PRCM_CONFIG_II 1
wdenk5a95f6f2005-01-12 00:38:03 +000043/*#define PRCM_CONFIG_III 1 */
wdenk289f9322005-01-12 00:15:14 +000044
45/* Memory configuration on board */
wdenk5a95f6f2005-01-12 00:38:03 +000046/*#define CONFIG_OPTIMIZE_DDR 1 */
wdenk8ed96042005-01-09 23:16:25 +000047
48#include <asm/arch/omap2420.h> /* get chip and board defs */
49
wdenk289f9322005-01-12 00:15:14 +000050/* On H4, NOR and NAND flash are mutual exclusive.
51 Define this if you want to use NAND
52 */
wdenk5a95f6f2005-01-12 00:38:03 +000053/*#define CFG_NAND_BOOT */
wdenk289f9322005-01-12 00:15:14 +000054
wdenk8ed96042005-01-09 23:16:25 +000055#ifdef CONFIG_APTIX
56#define V_SCLK 1500000
57#else
58#define V_SCLK 12000000
59#endif
60
61/* input clock of PLL */
62/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
63#define CONFIG_SYS_CLK_FREQ V_SCLK
64
65#undef CONFIG_USE_IRQ /* no support for IRQs */
66#define CONFIG_MISC_INIT_R
67
68#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
69#define CONFIG_SETUP_MEMORY_TAGS 1
70#define CONFIG_INITRD_TAG 1
wdenk289f9322005-01-12 00:15:14 +000071#define CONFIG_REVISION_TAG 1
wdenk8ed96042005-01-09 23:16:25 +000072
73/*
74 * Size of malloc() pool
75 */
76#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
77#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K)
78#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
79
80/*
81 * Hardware drivers
82 */
wdenk082acfd2005-01-10 00:01:04 +000083
wdenk8ed96042005-01-09 23:16:25 +000084/*
85 * SMC91c96 Etherent
86 */
87#define CONFIG_DRIVER_LAN91C96
88#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
89#define CONFIG_LAN91C96_EXT_PHY
90
91/*
92 * NS16550 Configuration
93 */
94#ifdef CONFIG_APTIX
95#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */
96#else
97#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
98#endif
99
100#define CFG_NS16550
101#define CFG_NS16550_SERIAL
102#define CFG_NS16550_REG_SIZE (-4)
103#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
104#define CFG_NS16550_COM1 OMAP2420_UART1
105
106/*
107 * select serial console configuration
108 */
109#define CONFIG_SERIAL1 1 /* UART1 on H4 */
110
111 /*
112 * I2C configuration
113 */
114#define CONFIG_HARD_I2C
115#define CFG_I2C_SPEED 100000
116#define CFG_I2C_SLAVE 1
117#define CONFIG_DRIVER_OMAP24XX_I2C
118
119/* allow to overwrite serial and ethaddr */
120#define CONFIG_ENV_OVERWRITE
121#define CONFIG_CONS_INDEX 1
122#define CONFIG_BAUDRATE 115200
123#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
124
wdenk289f9322005-01-12 00:15:14 +0000125#ifdef CFG_NAND_BOOT
126#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
127#else
128#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2)
129#endif
wdenk082acfd2005-01-10 00:01:04 +0000130/* I'd like to get to these. Snap kernel loads if we make MMC go */
131 /* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C) */
wdenk8ed96042005-01-09 23:16:25 +0000132
133#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
134
135/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
136#include <cmd_confdefs.h>
137
wdenk289f9322005-01-12 00:15:14 +0000138/*
139 * Board NAND Info.
140 */
141#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
142
143#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
144#define SECTORSIZE 512
145
146#define ADDR_COLUMN 1
147#define ADDR_PAGE 2
148#define ADDR_COLUMN_PAGE 3
149
150#define NAND_ChipID_UNKNOWN 0x00
151#define NAND_MAX_FLOORS 1
152#define NAND_MAX_CHIPS 1
153
154#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
155#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
156#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
157#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
158#define NAND_WAIT_READY(nand) udelay(10)
159
160#define NAND_NO_RB 1
161
162#define CFG_NAND_WP
163#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
164#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
165
166
167#define NAND_CTL_CLRALE(nandptr)
168#define NAND_CTL_SETALE(nandptr)
169#define NAND_CTL_CLRCLE(nandptr)
170#define NAND_CTL_SETCLE(nandptr)
171#define NAND_DISABLE_CE(nand)
172#define NAND_ENABLE_CE(nand)
173
174
wdenk8ed96042005-01-09 23:16:25 +0000175#define CONFIG_BOOTDELAY 3
176
177#ifdef NFS_BOOT_DEFAULTS
178#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
179#else
180#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
181#endif
182
183#define CONFIG_NETMASK 255.255.254.0
184#define CONFIG_IPADDR 128.247.77.90
185#define CONFIG_SERVERIP 128.247.77.158
186#define CONFIG_BOOTFILE "uImage"
187
188/*
189 * Miscellaneous configurable options
190 */
191#ifdef CONFIG_APTIX
192#define V_PROMPT "OMAP2420 Aptix # "
193#else
194#define V_PROMPT "OMAP242x H4 # "
195#endif
196
197#define CFG_LONGHELP /* undef to save memory */
198#define CFG_PROMPT V_PROMPT
199#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
200/* Print Buffer Size */
201#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
202#define CFG_MAXARGS 16 /* max number of command args */
203#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
204
205#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
206#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
207
208#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
209
210#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
211
212/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
213 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
214 */
215#ifdef CONFIG_APTIX
216#define V_PVT 3
217#else
218#define V_PVT 7 /* use with 12MHz/128 */
219#endif
220
221#define CFG_TIMERBASE OMAP2420_GPT2
222#define CFG_PVT V_PVT /* 2^(pvt+1) */
223#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
224
225/*-----------------------------------------------------------------------
226 * Stack sizes
227 *
228 * The stack sizes are set up in start.S using the settings below
229 */
230#define CONFIG_STACKSIZE SZ_128K /* regular stack */
231#ifdef CONFIG_USE_IRQ
232#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
233#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
234#endif
235
236/*-----------------------------------------------------------------------
237 * Physical Memory Map
238 */
239#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
240#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
241#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
242#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
243
244#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
245#define PHYS_FLASH_SIZE_1 SZ_32M
246#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
247#define PHYS_FLASH_SIZE_2 SZ_32M
248#define CFG_FLASH_BASE PHYS_FLASH_1
249
250/*-----------------------------------------------------------------------
251 * FLASH and environment organization
252 */
253#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
254#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
255
wdenk289f9322005-01-12 00:15:14 +0000256#ifdef CFG_NAND_BOOT
257#define CFG_ENV_IS_IN_NAND 1
258#define CFG_ENV_OFFSET 0x80000 /* environment starts here */
259#else
wdenk8ed96042005-01-09 23:16:25 +0000260#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K)
261#define CFG_ENV_IS_IN_FLASH 1
wdenk289f9322005-01-12 00:15:14 +0000262#endif
wdenk8ed96042005-01-09 23:16:25 +0000263
264/* timeout values are in ticks */
wdenk289f9322005-01-12 00:15:14 +0000265#define CFG_FLASH_ERASE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Erase */
266#define CFG_FLASH_WRITE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Write */
267
wdenk289f9322005-01-12 00:15:14 +0000268#define CFG_JFFS2_MEM_NAND
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200269
270/*
271 * JFFS2 partitions
272 */
273/* No command line, one static partition, whole device */
274#undef CONFIG_JFFS2_CMDLINE
275#define CONFIG_JFFS2_DEV "nor1"
276#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
277#define CONFIG_JFFS2_PART_OFFSET 0x00000000
278
279/* mtdparts command line support */
280/* Note: fake mtd_id used, no linux mtd map file */
281/*
282#define CONFIG_JFFS2_CMDLINE
283#define MTDIDS_DEFAULT "nor1=omap2420-1"
284#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
285*/
wdenk8ed96042005-01-09 23:16:25 +0000286
287#endif /* __CONFIG_H */