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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * Rick Bronson <rick@efn.org>
3 *
4 * Configuation settings for the AT91RM9200DK board.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/* ARM asynchronous clock */
wdenk8b07a112004-07-10 21:45:47 +000029#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
30#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
31/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
wdenkdc7c9a12003-03-26 06:55:25 +000032
wdenkd9df1f42004-03-15 09:00:01 +000033#define AT91_SLOW_CLOCK 32768 /* slow clock */
34
wdenka85f9f22005-04-06 13:52:31 +000035#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
36#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
37#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39#define USE_920T_MMU 1
40
wdenk8b07a112004-07-10 21:45:47 +000041#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenkdc7c9a12003-03-26 06:55:25 +000042#define CONFIG_SETUP_MEMORY_TAGS 1
wdenk8b07a112004-07-10 21:45:47 +000043#define CONFIG_INITRD_TAG 1
wdenk2abbe072003-06-16 23:50:08 +000044
wdenk8aa1a2d2005-04-04 12:44:11 +000045#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenkef2807c2005-03-31 23:44:33 +000046#define CFG_USE_MAIN_OSCILLATOR 1
47/* flash */
48#define MC_PUIA_VAL 0x00000000
49#define MC_PUP_VAL 0x00000000
50#define MC_PUER_VAL 0x00000000
51#define MC_ASR_VAL 0x00000000
52#define MC_AASR_VAL 0x00000000
53#define EBI_CFGR_VAL 0x00000000
54#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
55
56/* clocks */
57#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
58#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
59#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
60
61/* sdram */
62#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63#define PIOC_BSR_VAL 0x00000000
64#define PIOC_PDR_VAL 0xFFFF0000
65#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
66#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
67#define SDRAM 0x20000000 /* address of the SDRAM */
68#define SDRAM1 0x20000080 /* address of the SDRAM */
69#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
70#define SDRC_MR_VAL 0x00000002 /* Precharge All */
71#define SDRC_MR_VAL1 0x00000004 /* refresh */
72#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
wdenk8aa1a2d2005-04-04 12:44:11 +000075#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenkdc7c9a12003-03-26 06:55:25 +000076/*
77 * Size of malloc() pool
78 */
79#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenka8c7c702003-12-06 19:49:23 +000080#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
81
wdenkdc7c9a12003-03-26 06:55:25 +000082#define CONFIG_BAUDRATE 115200
wdenka8c7c702003-12-06 19:49:23 +000083
wdenkdc7c9a12003-03-26 06:55:25 +000084/*
85 * Hardware drivers
86 */
87
wdenk9d5028c2004-11-21 00:06:33 +000088/* define one of these to choose the DBGU, USART0 or USART1 as console */
wdenk4734cb72004-09-21 23:33:32 +000089#define CONFIG_DBGU
wdenk9d5028c2004-11-21 00:06:33 +000090#undef CONFIG_USART0
wdenk4734cb72004-09-21 23:33:32 +000091#undef CONFIG_USART1
92
wdenkdc7c9a12003-03-26 06:55:25 +000093#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
94
95#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
96
wdenk8bde7f72003-06-27 21:31:46 +000097#define CONFIG_BOOTDELAY 3
wdenk8b07a112004-07-10 21:45:47 +000098/* #define CONFIG_ENV_OVERWRITE 1 */
wdenk2abbe072003-06-16 23:50:08 +000099
wdenkdc7c9a12003-03-26 06:55:25 +0000100#define CONFIG_COMMANDS \
wdenk8b07a112004-07-10 21:45:47 +0000101 ((CONFIG_CMD_DFL | \
wdenk2abbe072003-06-16 23:50:08 +0000102 CFG_CMD_DHCP ) & \
wdenk8bde7f72003-06-27 21:31:46 +0000103 ~(CFG_CMD_BDI | \
104 CFG_CMD_IMI | \
105 CFG_CMD_AUTOSCRIPT | \
106 CFG_CMD_FPGA | \
107 CFG_CMD_MISC | \
108 CFG_CMD_LOADS ))
109
wdenkdc7c9a12003-03-26 06:55:25 +0000110/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
111#include <cmd_confdefs.h>
112
113#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
114#define SECTORSIZE 512
115
116#define ADDR_COLUMN 1
117#define ADDR_PAGE 2
118#define ADDR_COLUMN_PAGE 3
119
wdenk8b07a112004-07-10 21:45:47 +0000120#define NAND_ChipID_UNKNOWN 0x00
wdenkdc7c9a12003-03-26 06:55:25 +0000121#define NAND_MAX_FLOORS 1
122#define NAND_MAX_CHIPS 1
123
wdenk8b07a112004-07-10 21:45:47 +0000124#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
125#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
wdenkdc7c9a12003-03-26 06:55:25 +0000126
127#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
128#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
129
130#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
131
132#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
133#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
134#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
135#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
136/* the following are NOP's in our implementation */
137#define NAND_CTL_CLRALE(nandptr)
138#define NAND_CTL_SETALE(nandptr)
139#define NAND_CTL_CLRCLE(nandptr)
140#define NAND_CTL_SETCLE(nandptr)
141
142#define CONFIG_NR_DRAM_BANKS 1
143#define PHYS_SDRAM 0x20000000
144#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
145
wdenk8b07a112004-07-10 21:45:47 +0000146#define CFG_MEMTEST_START PHYS_SDRAM
147#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
wdenkdc7c9a12003-03-26 06:55:25 +0000148
149#define CONFIG_DRIVER_ETHER
wdenk8b07a112004-07-10 21:45:47 +0000150#define CONFIG_NET_RETRY_COUNT 20
wdenk074cff02004-02-24 00:16:43 +0000151#define CONFIG_AT91C_USE_RMII
wdenk2abbe072003-06-16 23:50:08 +0000152
wdenk8b07a112004-07-10 21:45:47 +0000153#define CONFIG_HAS_DATAFLASH 1
154#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
155#define CFG_MAX_DATAFLASH_BANKS 2
156#define CFG_MAX_DATAFLASH_PAGES 16384
wdenk2abbe072003-06-16 23:50:08 +0000157#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
158#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
wdenkdc7c9a12003-03-26 06:55:25 +0000159
wdenk8b07a112004-07-10 21:45:47 +0000160#define PHYS_FLASH_1 0x10000000
161#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
162#define CFG_FLASH_BASE PHYS_FLASH_1
163#define CFG_MAX_FLASH_BANKS 1
164#define CFG_MAX_FLASH_SECT 256
165#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
166#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
wdenk5779d8d2003-12-06 23:55:10 +0000167
168#undef CFG_ENV_IS_IN_DATAFLASH
169
170#ifdef CFG_ENV_IS_IN_DATAFLASH
wdenk8b07a112004-07-10 21:45:47 +0000171#define CFG_ENV_OFFSET 0x20000
172#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
173#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
wdenk5779d8d2003-12-06 23:55:10 +0000174#else
wdenk8b07a112004-07-10 21:45:47 +0000175#define CFG_ENV_IS_IN_FLASH 1
wdenk8aa1a2d2005-04-04 12:44:11 +0000176#ifdef CONFIG_SKIP_LOWLEVEL_INIT
wdenk9d5028c2004-11-21 00:06:33 +0000177#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
178#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
179#else
180#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
wdenk8b07a112004-07-10 21:45:47 +0000181#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
wdenk8aa1a2d2005-04-04 12:44:11 +0000182#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenk400558b2005-04-02 23:52:25 +0000183#endif /* CFG_ENV_IS_IN_DATAFLASH */
wdenk5779d8d2003-12-06 23:55:10 +0000184
185
wdenk8b07a112004-07-10 21:45:47 +0000186#define CFG_LOAD_ADDR 0x21000000 /* default load address */
wdenkdc7c9a12003-03-26 06:55:25 +0000187
wdenk8aa1a2d2005-04-04 12:44:11 +0000188#ifdef CONFIG_SKIP_LOWLEVEL_INIT
wdenk9d5028c2004-11-21 00:06:33 +0000189#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
190#define CFG_U_BOOT_BASE PHYS_FLASH_1
191#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */
192#else
wdenk2abbe072003-06-16 23:50:08 +0000193#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
wdenk8b07a112004-07-10 21:45:47 +0000194#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
195#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
wdenk8aa1a2d2005-04-04 12:44:11 +0000196#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenk2abbe072003-06-16 23:50:08 +0000197
wdenk8b07a112004-07-10 21:45:47 +0000198#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
wdenkdc7c9a12003-03-26 06:55:25 +0000199
wdenk8b07a112004-07-10 21:45:47 +0000200#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
201#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
202#define CFG_MAXARGS 16 /* max number of command args */
203#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenkdc7c9a12003-03-26 06:55:25 +0000204
205#ifndef __ASSEMBLY__
206/*-----------------------------------------------------------------------
207 * Board specific extension for bd_info
208 *
209 * This structure is embedded in the global bd_info (bd_t) structure
210 * and can be used by the board specific code (eg board/...)
211 */
212
wdenk8b07a112004-07-10 21:45:47 +0000213struct bd_info_ext {
214 /* helper variable for board environment handling
215 *
216 * env_crc_valid == 0 => uninitialised
217 * env_crc_valid > 0 => environment crc in flash is valid
218 * env_crc_valid < 0 => environment crc in flash is invalid
219 */
220 int env_crc_valid;
wdenkdc7c9a12003-03-26 06:55:25 +0000221};
222#endif
223
wdenk9455b7f2004-10-11 22:25:49 +0000224#define CFG_HZ 1000
225#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
wdenk8b07a112004-07-10 21:45:47 +0000226 /* AT91C_TC_TIMER_DIV1_CLOCK */
wdenkdc7c9a12003-03-26 06:55:25 +0000227
228#define CONFIG_STACKSIZE (32*1024) /* regular stack */
229
230#ifdef CONFIG_USE_IRQ
231#error CONFIG_USE_IRQ not supported
232#endif
233
234#endif