blob: 4faf1747a8a2fde7ad456c9a442620aed0d601a6 [file] [log] [blame]
Vikas Manochae66c49f2016-02-11 15:47:20 -08001/*
2 * (C) Copyright 2016
3 * Vikas Manocha, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/rcc.h>
11#include <asm/arch/stm32.h>
12#include <asm/arch/stm32_periph.h>
13
Michael Kurzbad51882017-01-22 16:04:24 +010014#define RCC_CR_HSION BIT(0)
15#define RCC_CR_HSEON BIT(16)
16#define RCC_CR_HSERDY BIT(17)
17#define RCC_CR_HSEBYP BIT(18)
18#define RCC_CR_CSSON BIT(19)
19#define RCC_CR_PLLON BIT(24)
20#define RCC_CR_PLLRDY BIT(25)
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090021
Michael Kurzbad51882017-01-22 16:04:24 +010022#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
23#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
24#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
25#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
26#define RCC_PLLCFGR_PLLSRC BIT(22)
27#define RCC_PLLCFGR_PLLM_SHIFT 0
28#define RCC_PLLCFGR_PLLN_SHIFT 6
29#define RCC_PLLCFGR_PLLP_SHIFT 16
30#define RCC_PLLCFGR_PLLQ_SHIFT 24
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090031
Michael Kurzbad51882017-01-22 16:04:24 +010032#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
33#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
34#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
35#define RCC_CFGR_SW0 BIT(0)
36#define RCC_CFGR_SW1 BIT(1)
37#define RCC_CFGR_SW_MASK GENMASK(1, 0)
38#define RCC_CFGR_SW_HSI 0
39#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
40#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
41#define RCC_CFGR_SWS0 BIT(2)
42#define RCC_CFGR_SWS1 BIT(3)
43#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
44#define RCC_CFGR_SWS_HSI 0
45#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
46#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
47#define RCC_CFGR_HPRE_SHIFT 4
48#define RCC_CFGR_PPRE1_SHIFT 10
49#define RCC_CFGR_PPRE2_SHIFT 13
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090050
51/*
52 * Offsets of some PWR registers
53 */
Michael Kurzbad51882017-01-22 16:04:24 +010054#define PWR_CR1_ODEN BIT(16)
55#define PWR_CR1_ODSWEN BIT(17)
56#define PWR_CSR1_ODRDY BIT(16)
57#define PWR_CSR1_ODSWRDY BIT(17)
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090058
59struct pll_psc {
60 u8 pll_m;
61 u16 pll_n;
62 u8 pll_p;
63 u8 pll_q;
64 u8 ahb_psc;
65 u8 apb1_psc;
66 u8 apb2_psc;
67};
68
Michael Kurzbad51882017-01-22 16:04:24 +010069#define AHB_PSC_1 0
70#define AHB_PSC_2 0x8
71#define AHB_PSC_4 0x9
72#define AHB_PSC_8 0xA
73#define AHB_PSC_16 0xB
74#define AHB_PSC_64 0xC
75#define AHB_PSC_128 0xD
76#define AHB_PSC_256 0xE
77#define AHB_PSC_512 0xF
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090078
Michael Kurzbad51882017-01-22 16:04:24 +010079#define APB_PSC_1 0
80#define APB_PSC_2 0x4
81#define APB_PSC_4 0x5
82#define APB_PSC_8 0x6
83#define APB_PSC_16 0x7
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090084
85#if !defined(CONFIG_STM32_HSE_HZ)
86#error "CONFIG_STM32_HSE_HZ not defined!"
87#else
88#if (CONFIG_STM32_HSE_HZ == 25000000)
89#if (CONFIG_SYS_CLK_FREQ == 200000000)
90/* 200 MHz */
91struct pll_psc sys_pll_psc = {
92 .pll_m = 25,
93 .pll_n = 400,
94 .pll_p = 2,
95 .pll_q = 8,
96 .ahb_psc = AHB_PSC_1,
97 .apb1_psc = APB_PSC_4,
98 .apb2_psc = APB_PSC_2
99};
100#endif
101#else
102#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
103#endif
104#endif
105
106int configure_clocks(void)
107{
108 /* Reset RCC configuration */
109 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
110 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
111 clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
112 | RCC_CR_PLLON));
113 writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
114 clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
115 writel(0, &STM32_RCC->cir); /* Disable all interrupts */
116
117 /* Configure for HSE+PLL operation */
118 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
119 while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
120 ;
121
122 setbits_le32(&STM32_RCC->cfgr, ((
123 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
124 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
125 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
126
127 /* Configure the main PLL */
128 uint32_t pllcfgr = 0;
129 pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
130 pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
131 pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
132 pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
133 pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
134 writel(pllcfgr, &STM32_RCC->pllcfgr);
135
136 /* Enable the main PLL */
137 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
138 while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
139 ;
140
141 /* Enable high performance mode, System frequency up to 200 MHz */
142 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
143 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
144 /* Infinite wait! */
145 while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
146 ;
147 /* Enable the Over-drive switch */
148 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
149 /* Infinite wait! */
150 while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
151 ;
152
153 stm32_flash_latency_cfg(5);
154 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
155 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
156
157 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
158 RCC_CFGR_SWS_PLL)
159 ;
160
161 return 0;
162}
163
164unsigned long clock_get(enum clock clck)
165{
166 u32 sysclk = 0;
167 u32 shift = 0;
168 /* Prescaler table lookups for clock computation */
169 u8 ahb_psc_table[16] = {
170 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
171 };
172 u8 apb_psc_table[8] = {
173 0, 0, 0, 0, 1, 2, 3, 4
174 };
175
176 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
177 RCC_CFGR_SWS_PLL) {
178 u16 pllm, plln, pllp;
179 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
180 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
181 >> RCC_PLLCFGR_PLLN_SHIFT);
182 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
183 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
184 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
185 }
186
187 switch (clck) {
188 case CLOCK_CORE:
189 return sysclk;
190 break;
191 case CLOCK_AHB:
192 shift = ahb_psc_table[(
193 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
194 >> RCC_CFGR_HPRE_SHIFT)];
195 return sysclk >>= shift;
196 break;
197 case CLOCK_APB1:
198 shift = apb_psc_table[(
199 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
200 >> RCC_CFGR_PPRE1_SHIFT)];
201 return sysclk >>= shift;
202 break;
203 case CLOCK_APB2:
204 shift = apb_psc_table[(
205 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
206 >> RCC_CFGR_PPRE2_SHIFT)];
207 return sysclk >>= shift;
208 break;
209 default:
210 return 0;
211 break;
212 }
213}
214
215
Vikas Manochae66c49f2016-02-11 15:47:20 -0800216void clock_setup(int peripheral)
217{
218 switch (peripheral) {
219 case USART1_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100220 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_USART1EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800221 break;
Vikas Manochae66c49f2016-02-11 15:47:20 -0800222 case GPIO_A_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100223 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800224 break;
225 case GPIO_B_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100226 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800227 break;
228 case GPIO_C_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100229 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800230 break;
231 case GPIO_D_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100232 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800233 break;
234 case GPIO_E_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100235 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800236 break;
237 case GPIO_F_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100238 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800239 break;
240 case GPIO_G_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100241 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800242 break;
243 case GPIO_H_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100244 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800245 break;
246 case GPIO_I_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100247 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800248 break;
249 case GPIO_J_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100250 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800251 break;
252 case GPIO_K_CLOCK_CFG:
Michael Kurzbad51882017-01-22 16:04:24 +0100253 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN);
Vikas Manochae66c49f2016-02-11 15:47:20 -0800254 break;
Michael Kurz081de092017-01-22 16:04:26 +0100255 case SYSCFG_CLOCK_CFG:
256 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
257 break;
258 case TIMER2_CLOCK_CFG:
259 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
260 break;
261 case FMC_CLOCK_CFG:
262 setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN);
263 break;
Vikas Manochae66c49f2016-02-11 15:47:20 -0800264 default:
265 break;
266 }
267}