blob: 5d426b524a1e10776e73940e16c0be70596a6e2a [file] [log] [blame]
Tom Warren2fc65e22013-01-28 13:32:07 +00001/*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _TEGRA114_H_
18#define _TEGRA114_H_
19
20#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
Tom Warrenb40f7342013-04-01 15:48:54 -070021#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
Tom Warren2fc65e22013-01-28 13:32:07 +000022
23#include <asm/arch-tegra/tegra.h>
24
25#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */
26
27#undef NVBOOTINFOTABLE_BCTSIZE
28#undef NVBOOTINFOTABLE_BCTPTR
29#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
30#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
31
32#define MAX_NUM_CPU 4
33
34#endif /* TEGRA114_H */