| Rajeshwari Shinde | 02cfce3 | 2012-10-25 19:49:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Samsung Electronics |
| 3 | * R. Chandrasekar <rcsekar@samsung.com> |
| 4 | * |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Rajeshwari Shinde | 02cfce3 | 2012-10-25 19:49:25 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __I2S_REGS_H__ |
| 9 | #define __I2S_REGS_H__ |
| 10 | |
| Dani Krishna Mohan | 5fb5b15 | 2013-09-11 16:38:49 +0530 | [diff] [blame] | 11 | #define CON_RESET (1 << 31) |
| Rajeshwari Shinde | 02cfce3 | 2012-10-25 19:49:25 +0000 | [diff] [blame] | 12 | #define CON_TXFIFO_FULL (1 << 8) |
| 13 | #define CON_TXCH_PAUSE (1 << 4) |
| 14 | #define CON_ACTIVE (1 << 0) |
| 15 | |
| Dani Krishna Mohan | 5fb5b15 | 2013-09-11 16:38:49 +0530 | [diff] [blame] | 16 | #define MOD_OP_CLK (3 << 30) |
| Rajeshwari Shinde | 02cfce3 | 2012-10-25 19:49:25 +0000 | [diff] [blame] | 17 | #define MOD_BLCP_SHIFT 24 |
| 18 | #define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) |
| 19 | #define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) |
| 20 | #define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) |
| 21 | #define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) |
| 22 | |
| 23 | #define MOD_BLC_16BIT (0 << 13) |
| 24 | #define MOD_BLC_8BIT (1 << 13) |
| 25 | #define MOD_BLC_24BIT (2 << 13) |
| 26 | #define MOD_BLC_MASK (3 << 13) |
| 27 | |
| 28 | #define MOD_SLAVE (1 << 11) |
| Dani Krishna Mohan | 5fb5b15 | 2013-09-11 16:38:49 +0530 | [diff] [blame] | 29 | #define MOD_RCLKSRC (0 << 10) |
| Rajeshwari Shinde | 02cfce3 | 2012-10-25 19:49:25 +0000 | [diff] [blame] | 30 | #define MOD_MASK (3 << 8) |
| 31 | #define MOD_LR_LLOW (0 << 7) |
| 32 | #define MOD_LR_RLOW (1 << 7) |
| 33 | #define MOD_SDF_IIS (0 << 5) |
| 34 | #define MOD_SDF_MSB (1 << 5) |
| 35 | #define MOD_SDF_LSB (2 << 5) |
| 36 | #define MOD_SDF_MASK (3 << 5) |
| 37 | #define MOD_RCLK_256FS (0 << 3) |
| 38 | #define MOD_RCLK_512FS (1 << 3) |
| 39 | #define MOD_RCLK_384FS (2 << 3) |
| 40 | #define MOD_RCLK_768FS (3 << 3) |
| 41 | #define MOD_RCLK_MASK (3 << 3) |
| 42 | #define MOD_BCLK_32FS (0 << 1) |
| 43 | #define MOD_BCLK_48FS (1 << 1) |
| 44 | #define MOD_BCLK_16FS (2 << 1) |
| 45 | #define MOD_BCLK_24FS (3 << 1) |
| 46 | #define MOD_BCLK_MASK (3 << 1) |
| 47 | |
| 48 | #define MOD_CDCLKCON (1 << 12) |
| 49 | |
| 50 | #define FIC_TXFLUSH (1 << 15) |
| 51 | #define FIC_RXFLUSH (1 << 7) |
| 52 | |
| Dani Krishna Mohan | 5fb5b15 | 2013-09-11 16:38:49 +0530 | [diff] [blame] | 53 | #define PSREN (1 << 15) |
| 54 | #define PSVAL (3 << 8) |
| 55 | |
| Rajeshwari Shinde | 02cfce3 | 2012-10-25 19:49:25 +0000 | [diff] [blame] | 56 | #endif /* __I2S_REGS_H__ */ |