| Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. |
| 3 | * Terry Lv <r65388@freescale.com> |
| 4 | * |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __FSL_SATA_H__ |
| 9 | #define __FSL_SATA_H__ |
| 10 | |
| 11 | #define DWC_AHSATA_MAX_CMD_SLOTS 32 |
| 12 | |
| 13 | /* Max host controller numbers */ |
| 14 | #define SATA_HC_MAX_NUM 4 |
| 15 | /* Max command queue depth per host controller */ |
| 16 | #define DWC_AHSATA_HC_MAX_CMD 32 |
| 17 | /* Max port number per host controller */ |
| 18 | #define SATA_HC_MAX_PORT 16 |
| 19 | |
| 20 | /* Generic Host Register */ |
| 21 | |
| 22 | /* HBA Capabilities Register */ |
| 23 | #define SATA_HOST_CAP_S64A 0x80000000 |
| 24 | #define SATA_HOST_CAP_SNCQ 0x40000000 |
| 25 | #define SATA_HOST_CAP_SSNTF 0x20000000 |
| 26 | #define SATA_HOST_CAP_SMPS 0x10000000 |
| 27 | #define SATA_HOST_CAP_SSS 0x08000000 |
| 28 | #define SATA_HOST_CAP_SALP 0x04000000 |
| 29 | #define SATA_HOST_CAP_SAL 0x02000000 |
| 30 | #define SATA_HOST_CAP_SCLO 0x01000000 |
| 31 | #define SATA_HOST_CAP_ISS_MASK 0x00f00000 |
| 32 | #define SATA_HOST_CAP_ISS_OFFSET 20 |
| 33 | #define SATA_HOST_CAP_SNZO 0x00080000 |
| 34 | #define SATA_HOST_CAP_SAM 0x00040000 |
| 35 | #define SATA_HOST_CAP_SPM 0x00020000 |
| 36 | #define SATA_HOST_CAP_PMD 0x00008000 |
| 37 | #define SATA_HOST_CAP_SSC 0x00004000 |
| 38 | #define SATA_HOST_CAP_PSC 0x00002000 |
| 39 | #define SATA_HOST_CAP_NCS 0x00001f00 |
| 40 | #define SATA_HOST_CAP_CCCS 0x00000080 |
| 41 | #define SATA_HOST_CAP_EMS 0x00000040 |
| 42 | #define SATA_HOST_CAP_SXS 0x00000020 |
| 43 | #define SATA_HOST_CAP_NP_MASK 0x0000001f |
| 44 | |
| 45 | /* Global HBA Control Register */ |
| 46 | #define SATA_HOST_GHC_AE 0x80000000 |
| 47 | #define SATA_HOST_GHC_IE 0x00000002 |
| 48 | #define SATA_HOST_GHC_HR 0x00000001 |
| 49 | |
| 50 | /* Interrupt Status Register */ |
| 51 | |
| 52 | /* Ports Implemented Register */ |
| 53 | |
| 54 | /* AHCI Version Register */ |
| 55 | #define SATA_HOST_VS_MJR_MASK 0xffff0000 |
| 56 | #define SATA_HOST_VS_MJR_OFFSET 16 |
| 57 | #define SATA_HOST_VS_MJR_MNR 0x0000ffff |
| 58 | |
| 59 | /* Command Completion Coalescing Control */ |
| 60 | #define SATA_HOST_CCC_CTL_TV_MASK 0xffff0000 |
| 61 | #define SATA_HOST_CCC_CTL_TV_OFFSET 16 |
| 62 | #define SATA_HOST_CCC_CTL_CC_MASK 0x0000ff00 |
| 63 | #define SATA_HOST_CCC_CTL_CC_OFFSET 8 |
| 64 | #define SATA_HOST_CCC_CTL_INT_MASK 0x000000f8 |
| 65 | #define SATA_HOST_CCC_CTL_INT_OFFSET 3 |
| 66 | #define SATA_HOST_CCC_CTL_EN 0x00000001 |
| 67 | |
| 68 | /* Command Completion Coalescing Ports */ |
| 69 | |
| 70 | /* HBA Capabilities Extended Register */ |
| 71 | #define SATA_HOST_CAP2_APST 0x00000004 |
| 72 | |
| 73 | /* BIST Activate FIS Register */ |
| 74 | #define SATA_HOST_BISTAFR_NCP_MASK 0x0000ff00 |
| 75 | #define SATA_HOST_BISTAFR_NCP_OFFSET 8 |
| 76 | #define SATA_HOST_BISTAFR_PD_MASK 0x000000ff |
| 77 | #define SATA_HOST_BISTAFR_PD_OFFSET 0 |
| 78 | |
| 79 | /* BIST Control Register */ |
| 80 | #define SATA_HOST_BISTCR_FERLB 0x00100000 |
| 81 | #define SATA_HOST_BISTCR_TXO 0x00040000 |
| 82 | #define SATA_HOST_BISTCR_CNTCLR 0x00020000 |
| 83 | #define SATA_HOST_BISTCR_NEALB 0x00010000 |
| 84 | #define SATA_HOST_BISTCR_LLC_MASK 0x00000700 |
| 85 | #define SATA_HOST_BISTCR_LLC_OFFSET 8 |
| 86 | #define SATA_HOST_BISTCR_ERREN 0x00000040 |
| 87 | #define SATA_HOST_BISTCR_FLIP 0x00000020 |
| 88 | #define SATA_HOST_BISTCR_PV 0x00000010 |
| 89 | #define SATA_HOST_BISTCR_PATTERN_MASK 0x0000000f |
| 90 | #define SATA_HOST_BISTCR_PATTERN_OFFSET 0 |
| 91 | |
| 92 | /* BIST FIS Count Register */ |
| 93 | |
| 94 | /* BIST Status Register */ |
| 95 | #define SATA_HOST_BISTSR_FRAMERR_MASK 0x0000ffff |
| 96 | #define SATA_HOST_BISTSR_FRAMERR_OFFSET 0 |
| 97 | #define SATA_HOST_BISTSR_BRSTERR_MASK 0x00ff0000 |
| 98 | #define SATA_HOST_BISTSR_BRSTERR_OFFSET 16 |
| 99 | |
| 100 | /* BIST DWORD Error Count Register */ |
| 101 | |
| 102 | /* OOB Register*/ |
| 103 | #define SATA_HOST_OOBR_WE 0x80000000 |
| 104 | #define SATA_HOST_OOBR_cwMin_MASK 0x7f000000 |
| 105 | #define SATA_HOST_OOBR_cwMAX_MASK 0x00ff0000 |
| 106 | #define SATA_HOST_OOBR_ciMin_MASK 0x0000ff00 |
| 107 | #define SATA_HOST_OOBR_ciMax_MASK 0x000000ff |
| 108 | |
| 109 | /* Timer 1-ms Register */ |
| 110 | |
| 111 | /* Global Parameter 1 Register */ |
| 112 | #define SATA_HOST_GPARAM1R_ALIGN_M 0x80000000 |
| 113 | #define SATA_HOST_GPARAM1R_RX_BUFFER 0x40000000 |
| 114 | #define SATA_HOST_GPARAM1R_PHY_DATA_MASK 0x30000000 |
| 115 | #define SATA_HOST_GPARAM1R_PHY_RST 0x08000000 |
| 116 | #define SATA_HOST_GPARAM1R_PHY_CTRL_MASK 0x07e00000 |
| 117 | #define SATA_HOST_GPARAM1R_PHY_STAT_MASK 0x001f8000 |
| 118 | #define SATA_HOST_GPARAM1R_LATCH_M 0x00004000 |
| 119 | #define SATA_HOST_GPARAM1R_BIST_M 0x00002000 |
| 120 | #define SATA_HOST_GPARAM1R_PHY_TYPE 0x00001000 |
| 121 | #define SATA_HOST_GPARAM1R_RETURN_ERR 0x00000400 |
| 122 | #define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK 0x00000300 |
| 123 | #define SATA_HOST_GPARAM1R_S_HADDR 0X00000080 |
| 124 | #define SATA_HOST_GPARAM1R_M_HADDR 0X00000040 |
| 125 | |
| 126 | /* Global Parameter 2 Register */ |
| 127 | #define SATA_HOST_GPARAM2R_DEV_CP 0x00004000 |
| 128 | #define SATA_HOST_GPARAM2R_DEV_MP 0x00002000 |
| 129 | #define SATA_HOST_GPARAM2R_DEV_ENCODE_M 0x00001000 |
| 130 | #define SATA_HOST_GPARAM2R_RXOOB_CLK_M 0x00000800 |
| 131 | #define SATA_HOST_GPARAM2R_RXOOB_M 0x00000400 |
| 132 | #define SATA_HOST_GPARAM2R_TX_OOB_M 0x00000200 |
| 133 | #define SATA_HOST_GPARAM2R_RXOOB_CLK_MASK 0x000001ff |
| 134 | |
| 135 | /* Port Parameter Register */ |
| 136 | #define SATA_HOST_PPARAMR_TX_MEM_M 0x00000200 |
| 137 | #define SATA_HOST_PPARAMR_TX_MEM_S 0x00000100 |
| 138 | #define SATA_HOST_PPARAMR_RX_MEM_M 0x00000080 |
| 139 | #define SATA_HOST_PPARAMR_RX_MEM_S 0x00000040 |
| 140 | #define SATA_HOST_PPARAMR_TXFIFO_DEPTH_MASK 0x00000038 |
| 141 | #define SATA_HOST_PPARAMR_RXFIFO_DEPTH_MASK 0x00000007 |
| 142 | |
| 143 | /* Test Register */ |
| 144 | #define SATA_HOST_TESTR_PSEL_MASK 0x00070000 |
| 145 | #define SATA_HOST_TESTR_TEST_IF 0x00000001 |
| 146 | |
| 147 | /* Port Register Descriptions */ |
| 148 | /* Port# Command List Base Address Register */ |
| 149 | #define SATA_PORT_CLB_CLB_MASK 0xfffffc00 |
| 150 | |
| 151 | /* Port# Command List Base Address Upper 32-Bits Register */ |
| 152 | |
| 153 | /* Port# FIS Base Address Register */ |
| 154 | #define SATA_PORT_FB_FB_MASK 0xfffffff0 |
| 155 | |
| 156 | /* Port# FIS Base Address Upper 32-Bits Register */ |
| 157 | |
| 158 | /* Port# Interrupt Status Register */ |
| 159 | #define SATA_PORT_IS_CPDS 0x80000000 |
| 160 | #define SATA_PORT_IS_TFES 0x40000000 |
| 161 | #define SATA_PORT_IS_HBFS 0x20000000 |
| 162 | #define SATA_PORT_IS_HBDS 0x10000000 |
| 163 | #define SATA_PORT_IS_IFS 0x08000000 |
| 164 | #define SATA_PORT_IS_INFS 0x04000000 |
| 165 | #define SATA_PORT_IS_OFS 0x01000000 |
| 166 | #define SATA_PORT_IS_IPMS 0x00800000 |
| 167 | #define SATA_PORT_IS_PRCS 0x00400000 |
| 168 | #define SATA_PORT_IS_DMPS 0x00000080 |
| 169 | #define SATA_PORT_IS_PCS 0x00000040 |
| 170 | #define SATA_PORT_IS_DPS 0x00000020 |
| 171 | #define SATA_PORT_IS_UFS 0x00000010 |
| 172 | #define SATA_PORT_IS_SDBS 0x00000008 |
| 173 | #define SATA_PORT_IS_DSS 0x00000004 |
| 174 | #define SATA_PORT_IS_PSS 0x00000002 |
| 175 | #define SATA_PORT_IS_DHRS 0x00000001 |
| 176 | |
| 177 | /* Port# Interrupt Enable Register */ |
| 178 | #define SATA_PORT_IE_CPDE 0x80000000 |
| 179 | #define SATA_PORT_IE_TFEE 0x40000000 |
| 180 | #define SATA_PORT_IE_HBFE 0x20000000 |
| 181 | #define SATA_PORT_IE_HBDE 0x10000000 |
| 182 | #define SATA_PORT_IE_IFE 0x08000000 |
| 183 | #define SATA_PORT_IE_INFE 0x04000000 |
| 184 | #define SATA_PORT_IE_OFE 0x01000000 |
| 185 | #define SATA_PORT_IE_IPME 0x00800000 |
| 186 | #define SATA_PORT_IE_PRCE 0x00400000 |
| 187 | #define SATA_PORT_IE_DMPE 0x00000080 |
| 188 | #define SATA_PORT_IE_PCE 0x00000040 |
| 189 | #define SATA_PORT_IE_DPE 0x00000020 |
| 190 | #define SATA_PORT_IE_UFE 0x00000010 |
| 191 | #define SATA_PORT_IE_SDBE 0x00000008 |
| 192 | #define SATA_PORT_IE_DSE 0x00000004 |
| 193 | #define SATA_PORT_IE_PSE 0x00000002 |
| 194 | #define SATA_PORT_IE_DHRE 0x00000001 |
| 195 | |
| 196 | /* Port# Command Register */ |
| 197 | #define SATA_PORT_CMD_ICC_MASK 0xf0000000 |
| 198 | #define SATA_PORT_CMD_ASP 0x08000000 |
| 199 | #define SATA_PORT_CMD_ALPE 0x04000000 |
| 200 | #define SATA_PORT_CMD_DLAE 0x02000000 |
| 201 | #define SATA_PORT_CMD_ATAPI 0x01000000 |
| 202 | #define SATA_PORT_CMD_APSTE 0x00800000 |
| 203 | #define SATA_PORT_CMD_ESP 0x00200000 |
| 204 | #define SATA_PORT_CMD_CPD 0x00100000 |
| 205 | #define SATA_PORT_CMD_MPSP 0x00080000 |
| 206 | #define SATA_PORT_CMD_HPCP 0x00040000 |
| 207 | #define SATA_PORT_CMD_PMA 0x00020000 |
| 208 | #define SATA_PORT_CMD_CPS 0x00010000 |
| 209 | #define SATA_PORT_CMD_CR 0x00008000 |
| 210 | #define SATA_PORT_CMD_FR 0x00004000 |
| 211 | #define SATA_PORT_CMD_MPSS 0x00002000 |
| 212 | #define SATA_PORT_CMD_CCS_MASK 0x00001f00 |
| 213 | #define SATA_PORT_CMD_FRE 0x00000010 |
| 214 | #define SATA_PORT_CMD_CLO 0x00000008 |
| 215 | #define SATA_PORT_CMD_POD 0x00000004 |
| 216 | #define SATA_PORT_CMD_SUD 0x00000002 |
| 217 | #define SATA_PORT_CMD_ST 0x00000001 |
| 218 | |
| 219 | /* Port# Task File Data Register */ |
| 220 | #define SATA_PORT_TFD_ERR_MASK 0x0000ff00 |
| 221 | #define SATA_PORT_TFD_STS_MASK 0x000000ff |
| 222 | #define SATA_PORT_TFD_STS_ERR 0x00000001 |
| 223 | #define SATA_PORT_TFD_STS_DRQ 0x00000008 |
| 224 | #define SATA_PORT_TFD_STS_BSY 0x00000080 |
| 225 | |
| 226 | /* Port# Signature Register */ |
| 227 | |
| 228 | /* Port# Serial ATA Status {SStatus} Register */ |
| 229 | #define SATA_PORT_SSTS_IPM_MASK 0x00000f00 |
| 230 | #define SATA_PORT_SSTS_SPD_MASK 0x000000f0 |
| 231 | #define SATA_PORT_SSTS_DET_MASK 0x0000000f |
| 232 | |
| 233 | /* Port# Serial ATA Control {SControl} Register */ |
| 234 | #define SATA_PORT_SCTL_IPM_MASK 0x00000f00 |
| 235 | #define SATA_PORT_SCTL_SPD_MASK 0x000000f0 |
| 236 | #define SATA_PORT_SCTL_DET_MASK 0x0000000f |
| 237 | |
| 238 | /* Port# Serial ATA Error {SError} Register */ |
| 239 | #define SATA_PORT_SERR_DIAG_X 0x04000000 |
| 240 | #define SATA_PORT_SERR_DIAG_F 0x02000000 |
| 241 | #define SATA_PORT_SERR_DIAG_T 0x01000000 |
| 242 | #define SATA_PORT_SERR_DIAG_S 0x00800000 |
| 243 | #define SATA_PORT_SERR_DIAG_H 0x00400000 |
| 244 | #define SATA_PORT_SERR_DIAG_C 0x00200000 |
| 245 | #define SATA_PORT_SERR_DIAG_D 0x00100000 |
| 246 | #define SATA_PORT_SERR_DIAG_B 0x00080000 |
| 247 | #define SATA_PORT_SERR_DIAG_W 0x00040000 |
| 248 | #define SATA_PORT_SERR_DIAG_I 0x00020000 |
| 249 | #define SATA_PORT_SERR_DIAG_N 0x00010000 |
| 250 | #define SATA_PORT_SERR_ERR_E 0x00000800 |
| 251 | #define SATA_PORT_SERR_ERR_P 0x00000400 |
| 252 | #define SATA_PORT_SERR_ERR_C 0x00000200 |
| 253 | #define SATA_PORT_SERR_ERR_T 0x00000100 |
| 254 | #define SATA_PORT_SERR_ERR_M 0x00000002 |
| 255 | #define SATA_PORT_SERR_ERR_I 0x00000001 |
| 256 | |
| 257 | /* Port# Serial ATA Active {SActive} Register */ |
| 258 | |
| 259 | /* Port# Command Issue Register */ |
| 260 | |
| 261 | /* Port# Serial ATA Notification Register */ |
| 262 | |
| 263 | /* Port# DMA Control Register */ |
| 264 | #define SATA_PORT_DMACR_RXABL_MASK 0x0000f000 |
| 265 | #define SATA_PORT_DMACR_TXABL_MASK 0x00000f00 |
| 266 | #define SATA_PORT_DMACR_RXTS_MASK 0x000000f0 |
| 267 | #define SATA_PORT_DMACR_TXTS_MASK 0x0000000f |
| 268 | |
| 269 | /* Port# PHY Control Register */ |
| 270 | |
| 271 | /* Port# PHY Status Register */ |
| 272 | |
| 273 | #define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry) |
| 274 | |
| 275 | /* DW0 |
| 276 | */ |
| 277 | #define CMD_HDR_DI_CFL_MASK 0x0000001f |
| 278 | #define CMD_HDR_DI_CFL_OFFSET 0 |
| 279 | #define CMD_HDR_DI_A 0x00000020 |
| 280 | #define CMD_HDR_DI_W 0x00000040 |
| 281 | #define CMD_HDR_DI_P 0x00000080 |
| 282 | #define CMD_HDR_DI_R 0x00000100 |
| 283 | #define CMD_HDR_DI_B 0x00000200 |
| 284 | #define CMD_HDR_DI_C 0x00000400 |
| 285 | #define CMD_HDR_DI_PMP_MASK 0x0000f000 |
| 286 | #define CMD_HDR_DI_PMP_OFFSET 12 |
| 287 | #define CMD_HDR_DI_PRDTL 0xffff0000 |
| 288 | #define CMD_HDR_DI_PRDTL_OFFSET 16 |
| 289 | |
| 290 | /* prde_fis_len |
| 291 | */ |
| 292 | #define CMD_HDR_PRD_ENTRY_SHIFT 16 |
| 293 | #define CMD_HDR_PRD_ENTRY_MASK 0x003f0000 |
| 294 | #define CMD_HDR_FIS_LEN_SHIFT 2 |
| 295 | |
| 296 | /* attribute |
| 297 | */ |
| 298 | #define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */ |
| 299 | #define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */ |
| 300 | /* Snoop enable for all descriptor */ |
| 301 | #define CMD_HDR_ATTR_SNOOP 0x00000200 |
| 302 | #define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */ |
| 303 | #define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */ |
| 304 | /* BIST - require the host to enter BIST mode */ |
| 305 | #define CMD_HDR_ATTR_BIST 0x00000040 |
| 306 | #define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */ |
| 307 | #define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */ |
| 308 | |
| 309 | #define FLAGS_DMA 0x00000000 |
| 310 | #define FLAGS_FPDMA 0x00000001 |
| 311 | |
| 312 | #define SATA_FLAG_Q_DEP_MASK 0x0000000f |
| 313 | #define SATA_FLAG_WCACHE 0x00000100 |
| 314 | #define SATA_FLAG_FLUSH 0x00000200 |
| 315 | #define SATA_FLAG_FLUSH_EXT 0x00000400 |
| 316 | |
| 317 | #define READ_CMD 0 |
| 318 | #define WRITE_CMD 1 |
| 319 | |
| Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 320 | #endif /* __FSL_SATA_H__ */ |