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gerrit.cesnet.cz / github / trini / u-boot / 06974ea0e3357823d38da0e18921c5ed5fe6d510 / . / arch / arm / dts / dra72-evm.dts
blob: 277745fec998657f5935e8e4fa3d6f3117cb161b [file] [log] [blame]
Tom Rini57cd6812015-07-31 19:55:12 -0400[diff] [blame]1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra72x.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14 model = "TI DRA722";
15 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
16
17 chosen {
18 stdout-path = &uart1;
Mugunthan V N6c3401a2015-12-24 16:08:19 +0530[diff] [blame]19 tick-timer = &timer2;
Tom Rini57cd6812015-07-31 19:55:12 -0400[diff] [blame]20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x40000000>; /* 1024 MB */
25 };
26
27 aliases {
28 display0 = &hdmi0;
29 };
30
31 evm_3v3: fixedregulator-evm_3v3 {
32 compatible = "regulator-fixed";
33 regulator-name = "evm_3v3";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 };
37
38 extcon_usb1: extcon_usb1 {
39 compatible = "linux,extcon-usb-gpio";
40 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
41 };
42
43 extcon_usb2: extcon_usb2 {
44 compatible = "linux,extcon-usb-gpio";
45 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
46 };
47
48 hdmi0: connector {
49 compatible = "hdmi-connector";
50 label = "hdmi";
51
52 type = "a";
53
54 port {
55 hdmi_connector_in: endpoint {
56 remote-endpoint = <&tpd12s015_out>;
57 };
58 };
59 };
60
61 tpd12s015: encoder {
62 compatible = "ti,tpd12s015";
63
64 pinctrl-names = "default";
65 pinctrl-0 = <&tpd12s015_pins>;
66
67 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
68 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
69 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
70
71 ports {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
75 port@0 {
76 reg = <0>;
77
78 tpd12s015_in: endpoint {
79 remote-endpoint = <&hdmi_out>;
80 };
81 };
82
83 port@1 {
84 reg = <1>;
85
86 tpd12s015_out: endpoint {
87 remote-endpoint = <&hdmi_connector_in>;
88 };
89 };
90 };
91 };
92};
93
94&dra7_pmx_core {
95 i2c1_pins: pinmux_i2c1_pins {
96 pinctrl-single,pins = <
97 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
98 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
99 >;
100 };
101
102 i2c5_pins: pinmux_i2c5_pins {
103 pinctrl-single,pins = <
104 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
105 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
106 >;
107 };
108
109 nand_default: nand_default {
110 pinctrl-single,pins = <
111 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
112 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
113 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
114 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
115 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
116 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
117 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
118 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
119 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
120 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
121 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
122 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
123 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
124 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
125 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
126 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
127 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
128 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
129 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
130 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
131 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
132 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
133 >;
134 };
135
136 usb1_pins: pinmux_usb1_pins {
137 pinctrl-single,pins = <
138 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
139 >;
140 };
141
142 usb2_pins: pinmux_usb2_pins {
143 pinctrl-single,pins = <
144 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
145 >;
146 };
147
148 tps65917_pins_default: tps65917_pins_default {
149 pinctrl-single,pins = <
150 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
151 >;
152 };
153
154 mmc1_pins_default: mmc1_pins_default {
155 pinctrl-single,pins = <
156 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
157 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
158 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
159 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
160 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
161 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
162 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
163 >;
164 };
165
166 mmc2_pins_default: mmc2_pins_default {
167 pinctrl-single,pins = <
168 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
169 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
170 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
171 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
172 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
173 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
174 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
175 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
176 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
177 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
178 >;
179 };
180
181 dcan1_pins_default: dcan1_pins_default {
182 pinctrl-single,pins = <
183 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
184 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
185 >;
186 };
187
188 dcan1_pins_sleep: dcan1_pins_sleep {
189 pinctrl-single,pins = <
190 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
191 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
192 >;
193 };
194
195 qspi1_pins: pinmux_qspi1_pins {
196 pinctrl-single,pins = <
197 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
198 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
199 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
200 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
201 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
202 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
203 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
204 >;
205 };
206
207 hdmi_pins: pinmux_hdmi_pins {
208 pinctrl-single,pins = <
209 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
210 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
211 >;
212 };
213
214 tpd12s015_pins: pinmux_tpd12s015_pins {
215 pinctrl-single,pins = <
216 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
217 >;
218 };
219};
220
221&i2c1 {
222 status = "okay";
223 pinctrl-names = "default";
224 pinctrl-0 = <&i2c1_pins>;
225 clock-frequency = <400000>;
226
227 tps65917: tps65917@58 {
228 compatible = "ti,tps65917";
229 reg = <0x58>;
230
231 pinctrl-names = "default";
232 pinctrl-0 = <&tps65917_pins_default>;
233
234 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
235 interrupt-controller;
236 #interrupt-cells = <2>;
237
238 ti,system-power-controller;
239
240 tps65917_pmic {
241 compatible = "ti,tps65917-pmic";
242
243 regulators {
244 smps1_reg: smps1 {
245 /* VDD_MPU */
246 regulator-name = "smps1";
247 regulator-min-microvolt = <850000>;
248 regulator-max-microvolt = <1250000>;
249 regulator-always-on;
250 regulator-boot-on;
251 };
252
253 smps2_reg: smps2 {
254 /* VDD_CORE */
255 regulator-name = "smps2";
256 regulator-min-microvolt = <850000>;
257 regulator-max-microvolt = <1060000>;
258 regulator-boot-on;
259 regulator-always-on;
260 };
261
262 smps3_reg: smps3 {
263 /* VDD_GPU IVA DSPEVE */
264 regulator-name = "smps3";
265 regulator-min-microvolt = <850000>;
266 regulator-max-microvolt = <1250000>;
267 regulator-boot-on;
268 regulator-always-on;
269 };
270
271 smps4_reg: smps4 {
272 /* VDDS1V8 */
273 regulator-name = "smps4";
274 regulator-min-microvolt = <1800000>;
275 regulator-max-microvolt = <1800000>;
276 regulator-always-on;
277 regulator-boot-on;
278 };
279
280 smps5_reg: smps5 {
281 /* VDD_DDR */
282 regulator-name = "smps5";
283 regulator-min-microvolt = <1350000>;
284 regulator-max-microvolt = <1350000>;
285 regulator-boot-on;
286 regulator-always-on;
287 };
288
289 ldo1_reg: ldo1 {
290 /* LDO1_OUT --> SDIO */
291 regulator-name = "ldo1";
292 regulator-min-microvolt = <1800000>;
293 regulator-max-microvolt = <3300000>;
294 regulator-boot-on;
295 };
296
297 ldo2_reg: ldo2 {
298 /* LDO2_OUT --> TP1017 (UNUSED) */
299 regulator-name = "ldo2";
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <3300000>;
302 };
303
304 ldo3_reg: ldo3 {
305 /* VDDA_1V8_PHY */
306 regulator-name = "ldo3";
307 regulator-min-microvolt = <1800000>;
308 regulator-max-microvolt = <1800000>;
309 regulator-boot-on;
310 regulator-always-on;
311 };
312
313 ldo5_reg: ldo5 {
314 /* VDDA_1V8_PLL */
315 regulator-name = "ldo5";
316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <1800000>;
318 regulator-always-on;
319 regulator-boot-on;
320 };
321
322 ldo4_reg: ldo4 {
323 /* VDDA_3V_USB: VDDA_USBHS33 */
324 regulator-name = "ldo4";
325 regulator-min-microvolt = <3300000>;
326 regulator-max-microvolt = <3300000>;
327 regulator-boot-on;
328 };
329 };
330 };
331
332 tps65917_power_button {
333 compatible = "ti,palmas-pwrbutton";
334 interrupt-parent = <&tps65917>;
335 interrupts = <1 IRQ_TYPE_NONE>;
336 wakeup-source;
337 ti,palmas-long-press-seconds = <6>;
338 };
339 };
340
341 pcf_gpio_21: gpio@21 {
342 compatible = "ti,pcf8575";
343 reg = <0x21>;
344 lines-initial-states = <0x1408>;
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-parent = <&gpio6>;
348 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
Vignesh R06974ea2016-08-02 10:14:26 +0530[diff] [blame^]351 u-boot,i2c-offset-len = <0>;
Tom Rini57cd6812015-07-31 19:55:12 -0400[diff] [blame]352 };
353};
354
355&i2c5 {
356 status = "okay";
357 pinctrl-names = "default";
358 pinctrl-0 = <&i2c5_pins>;
359 clock-frequency = <400000>;
360
361 pcf_hdmi: pcf8575@26 {
362 compatible = "nxp,pcf8575";
363 reg = <0x26>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 /*
367 * initial state is used here to keep the mdio interface
368 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
369 * VIN2_S0 driven high otherwise Ethernet stops working
370 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
371 */
372 lines-initial-states = <0x0f2b>;
Vignesh R06974ea2016-08-02 10:14:26 +0530[diff] [blame^]373 u-boot,i2c-offset-len = <0>;
Tom Rini57cd6812015-07-31 19:55:12 -0400[diff] [blame]374 };
375};
376
377&uart1 {
378 status = "okay";
379};
380
381&elm {
382 status = "okay";
383};
384
385&gpmc {
386 status = "okay";
387 pinctrl-names = "default";
388 pinctrl-0 = <&nand_default>;
389 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
390 nand@0,0 {
391 /* To use NAND, DIP switch SW5 must be set like so:
392 * SW5.1 (NAND_SELn) = ON (LOW)
393 * SW5.9 (GPMC_WPN) = OFF (HIGH)
394 */
395 reg = <0 0 4>; /* device IO registers */
396 ti,nand-ecc-opt = "bch8";
397 ti,elm-id = <&elm>;
398 nand-bus-width = <16>;
399 gpmc,device-width = <2>;
400 gpmc,sync-clk-ps = <0>;
401 gpmc,cs-on-ns = <0>;
402 gpmc,cs-rd-off-ns = <80>;
403 gpmc,cs-wr-off-ns = <80>;
404 gpmc,adv-on-ns = <0>;
405 gpmc,adv-rd-off-ns = <60>;
406 gpmc,adv-wr-off-ns = <60>;
407 gpmc,we-on-ns = <10>;
408 gpmc,we-off-ns = <50>;
409 gpmc,oe-on-ns = <4>;
410 gpmc,oe-off-ns = <40>;
411 gpmc,access-ns = <40>;
412 gpmc,wr-access-ns = <80>;
413 gpmc,rd-cycle-ns = <80>;
414 gpmc,wr-cycle-ns = <80>;
415 gpmc,bus-turnaround-ns = <0>;
416 gpmc,cycle2cycle-delay-ns = <0>;
417 gpmc,clk-activation-ns = <0>;
418 gpmc,wait-monitoring-ns = <0>;
419 gpmc,wr-data-mux-bus-ns = <0>;
420 /* MTD partition table */
421 /* All SPL-* partitions are sized to minimal length
422 * which can be independently programmable. For
423 * NAND flash this is equal to size of erase-block */
424 #address-cells = <1>;
425 #size-cells = <1>;
426 partition@0 {
427 label = "NAND.SPL";
428 reg = <0x00000000 0x000020000>;
429 };
430 partition@1 {
431 label = "NAND.SPL.backup1";
432 reg = <0x00020000 0x00020000>;
433 };
434 partition@2 {
435 label = "NAND.SPL.backup2";
436 reg = <0x00040000 0x00020000>;
437 };
438 partition@3 {
439 label = "NAND.SPL.backup3";
440 reg = <0x00060000 0x00020000>;
441 };
442 partition@4 {
443 label = "NAND.u-boot-spl-os";
444 reg = <0x00080000 0x00040000>;
445 };
446 partition@5 {
447 label = "NAND.u-boot";
448 reg = <0x000c0000 0x00100000>;
449 };
450 partition@6 {
451 label = "NAND.u-boot-env";
452 reg = <0x001c0000 0x00020000>;
453 };
454 partition@7 {
455 label = "NAND.u-boot-env.backup1";
456 reg = <0x001e0000 0x00020000>;
457 };
458 partition@8 {
459 label = "NAND.kernel";
460 reg = <0x00200000 0x00800000>;
461 };
462 partition@9 {
463 label = "NAND.file-system";
464 reg = <0x00a00000 0x0f600000>;
465 };
466 };
467};
468
469&usb2_phy1 {
470 phy-supply = <&ldo4_reg>;
471};
472
473&usb2_phy2 {
474 phy-supply = <&ldo4_reg>;
475};
476
477&omap_dwc3_1 {
478 extcon = <&extcon_usb1>;
479};
480
481&omap_dwc3_2 {
482 extcon = <&extcon_usb2>;
483};
484
485&usb1 {
486 dr_mode = "peripheral";
487 pinctrl-names = "default";
488 pinctrl-0 = <&usb1_pins>;
489};
490
491&usb2 {
492 dr_mode = "host";
493 pinctrl-names = "default";
494 pinctrl-0 = <&usb2_pins>;
495};
496
497&mmc1 {
498 status = "okay";
499 pinctrl-names = "default";
500 pinctrl-0 = <&mmc1_pins_default>;
501
502 vmmc-supply = <&ldo1_reg>;
503 bus-width = <4>;
504 /*
505 * SDCD signal is not being used here - using the fact that GPIO mode
506 * is a viable alternative
507 */
Mugunthan V Ne3614212016-04-04 17:28:03 +0530[diff] [blame]508 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
Tom Rini57cd6812015-07-31 19:55:12 -0400[diff] [blame]509};
510
511&mmc2 {
512 /* SW5-3 in ON position */
513 status = "okay";
514 pinctrl-names = "default";
515 pinctrl-0 = <&mmc2_pins_default>;
516
517 vmmc-supply = <&evm_3v3>;
518 bus-width = <8>;
519 ti,non-removable;
520};
521
522&dra7_pmx_core {
523 cpsw_default: cpsw_default {
524 pinctrl-single,pins = <
525 /* Slave 2 */
526 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
527 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
528 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
529 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
530 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
531 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
532 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
533 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
534 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
535 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
536 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
537 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
538 >;
539
540 };
541
542 cpsw_sleep: cpsw_sleep {
543 pinctrl-single,pins = <
544 /* Slave 2 */
545 0x198 (MUX_MODE15)
546 0x19c (MUX_MODE15)
547 0x1a0 (MUX_MODE15)
548 0x1a4 (MUX_MODE15)
549 0x1a8 (MUX_MODE15)
550 0x1ac (MUX_MODE15)
551 0x1b0 (MUX_MODE15)
552 0x1b4 (MUX_MODE15)
553 0x1b8 (MUX_MODE15)
554 0x1bc (MUX_MODE15)
555 0x1c0 (MUX_MODE15)
556 0x1c4 (MUX_MODE15)
557 >;
558 };
559
560 davinci_mdio_default: davinci_mdio_default {
561 pinctrl-single,pins = <
562 /* MDIO */
563 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
564 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
565 >;
566 };
567
568 davinci_mdio_sleep: davinci_mdio_sleep {
569 pinctrl-single,pins = <
570 0x23c (MUX_MODE15)
571 0x240 (MUX_MODE15)
572 >;
573 };
574};
575
576&mac {
577 status = "okay";
578 pinctrl-names = "default", "sleep";
579 pinctrl-0 = <&cpsw_default>;
580 pinctrl-1 = <&cpsw_sleep>;
581};
582
583&cpsw_emac1 {
584 phy_id = <&davinci_mdio>, <3>;
585 phy-mode = "rgmii";
586};
587
588&davinci_mdio {
589 pinctrl-names = "default", "sleep";
590 pinctrl-0 = <&davinci_mdio_default>;
591 pinctrl-1 = <&davinci_mdio_sleep>;
592 active_slave = <1>;
593};
594
595&dcan1 {
596 status = "ok";
597 pinctrl-names = "default", "sleep", "active";
598 pinctrl-0 = <&dcan1_pins_sleep>;
599 pinctrl-1 = <&dcan1_pins_sleep>;
600 pinctrl-2 = <&dcan1_pins_default>;
601};
602
603&qspi {
604 status = "okay";
605 pinctrl-names = "default";
606 pinctrl-0 = <&qspi1_pins>;
607
Vignesh R70ebdd72016-07-25 15:45:47 +0530[diff] [blame]608 spi-max-frequency = <76800000>;
Tom Rini57cd6812015-07-31 19:55:12 -0400[diff] [blame]609 m25p80@0 {
Mugunthan V N1f19d502015-12-23 20:39:44 +0530[diff] [blame]610 compatible = "s25fl256s1","spi-flash";
Vignesh Re835a742016-07-06 10:26:03 +0530[diff] [blame]611 spi-max-frequency = <64000000>;
Tom Rini57cd6812015-07-31 19:55:12 -0400[diff] [blame]612 reg = <0>;
613 spi-tx-bus-width = <1>;
614 spi-rx-bus-width = <4>;
Tom Rini57cd6812015-07-31 19:55:12 -0400[diff] [blame]615 #address-cells = <1>;
616 #size-cells = <1>;
617
618 /* MTD partition table.
619 * The ROM checks the first four physical blocks
620 * for a valid file to boot and the flash here is
621 * 64KiB block size.
622 */
623 partition@0 {
624 label = "QSPI.SPL";
625 reg = <0x00000000 0x000010000>;
626 };
627 partition@1 {
628 label = "QSPI.SPL.backup1";
629 reg = <0x00010000 0x00010000>;
630 };
631 partition@2 {
632 label = "QSPI.SPL.backup2";
633 reg = <0x00020000 0x00010000>;
634 };
635 partition@3 {
636 label = "QSPI.SPL.backup3";
637 reg = <0x00030000 0x00010000>;
638 };
639 partition@4 {
640 label = "QSPI.u-boot";
641 reg = <0x00040000 0x00100000>;
642 };
643 partition@5 {
644 label = "QSPI.u-boot-spl-os";
645 reg = <0x00140000 0x00080000>;
646 };
647 partition@6 {
648 label = "QSPI.u-boot-env";
649 reg = <0x001c0000 0x00010000>;
650 };
651 partition@7 {
652 label = "QSPI.u-boot-env.backup1";
653 reg = <0x001d0000 0x0010000>;
654 };
655 partition@8 {
656 label = "QSPI.kernel";
657 reg = <0x001e0000 0x0800000>;
658 };
659 partition@9 {
660 label = "QSPI.file-system";
661 reg = <0x009e0000 0x01620000>;
662 };
663 };
664};
665
666&dss {
667 status = "ok";
668
669 vdda_video-supply = <&ldo5_reg>;
670};
671
672&hdmi {
673 status = "ok";
674 vdda-supply = <&ldo3_reg>;
675
676 pinctrl-names = "default";
677 pinctrl-0 = <&hdmi_pins>;
678
679 port {
680 hdmi_out: endpoint {
681 remote-endpoint = <&tpd12s015_in>;
682 };
683 };
684};