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Stefan Roese17ceb062008-06-02 14:59:21 +02001/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef _PPC4xx_SDRAM_H_
25#define _PPC4xx_SDRAM_H_
26
27#if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM)
28
29/*
30 * SDRAM Controller
31 */
Adam Grahamf6b6c452008-09-03 12:26:59 -070032
Stefan Roese17ceb062008-06-02 14:59:21 +020033#ifndef CONFIG_405EP
Stefan Roese95b602b2009-09-24 13:59:57 +020034#define SDRAM0_BESR0 0x00 /* bus error syndrome reg a */
35#define SDRAM0_BESRS0 0x04 /* bus error syndrome reg set a */
36#define SDRAM0_BESR1 0x08 /* bus error syndrome reg b */
37#define SDRAM0_BESRS1 0x0c /* bus error syndrome reg set b */
38#define SDRAM0_BEAR 0x10 /* bus error address reg */
Stefan Roese17ceb062008-06-02 14:59:21 +020039#endif
Stefan Roese95b602b2009-09-24 13:59:57 +020040#define SDRAM0_CFG 0x20 /* memory controller options 1 */
41#define SDRAM0_STATUS 0x24 /* memory status */
42#define SDRAM0_RTR 0x30 /* refresh timer reg */
43#define SDRAM0_PMIT 0x34 /* power management idle timer */
44#define SDRAM0_B0CR 0x40 /* memory bank 0 configuration */
45#define SDRAM0_B1CR 0x44 /* memory bank 1 configuration */
Stefan Roese17ceb062008-06-02 14:59:21 +020046#ifndef CONFIG_405EP
Stefan Roese95b602b2009-09-24 13:59:57 +020047#define SDRAM0_B2CR 0x48 /* memory bank 2 configuration */
48#define SDRAM0_B3CR 0x4c /* memory bank 3 configuration */
Stefan Roese17ceb062008-06-02 14:59:21 +020049#endif
Stefan Roese95b602b2009-09-24 13:59:57 +020050#define SDRAM0_TR 0x80 /* timing reg 1 */
Stefan Roese17ceb062008-06-02 14:59:21 +020051#ifndef CONFIG_405EP
Stefan Roese95b602b2009-09-24 13:59:57 +020052#define SDRAM0_ECCCFG 0x94 /* ECC configuration */
53#define SDRAM0_ECCESR 0x98 /* ECC error status */
Stefan Roese17ceb062008-06-02 14:59:21 +020054#endif
55
56#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
57
58#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
59
60/*
61 * Memory controller registers
62 */
63#define SDRAM_CFG0 0x20 /* memory controller options 0 */
64#define SDRAM_CFG1 0x21 /* memory controller options 1 */
65
Stefan Roese95b602b2009-09-24 13:59:57 +020066#define SDRAM0_BEAR 0x0010 /* bus error address reg */
67#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
68#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */
69#define SDRAM0_CFG1 0x0021 /* ddr sdram options 1 */
70#define SDRAM0_DEVOPT 0x0022 /* ddr sdram device options */
71#define SDRAM0_MCSTS 0x0024 /* memory controller status */
72#define SDRAM0_RTR 0x0030 /* refresh timer register */
73#define SDRAM0_PMIT 0x0034 /* power management idle timer */
74#define SDRAM0_UABBA 0x0038 /* plb UABus base address */
75#define SDRAM0_B0CR 0x0040 /* ddr sdram bank 0 configuration */
76#define SDRAM0_B1CR 0x0044 /* ddr sdram bank 1 configuration */
77#define SDRAM0_B2CR 0x0048 /* ddr sdram bank 2 configuration */
78#define SDRAM0_B3CR 0x004c /* ddr sdram bank 3 configuration */
79#define SDRAM0_TR0 0x0080 /* sdram timing register 0 */
80#define SDRAM0_TR1 0x0081 /* sdram timing register 1 */
81#define SDRAM0_CLKTR 0x0082 /* ddr clock timing register */
82#define SDRAM0_WDDCTR 0x0083 /* write data/dm/dqs clock timing reg */
83#define SDRAM0_DLYCAL 0x0084 /* delay line calibration register */
84#define SDRAM0_ECCESR 0x0098 /* ECC error status */
Stefan Roese17ceb062008-06-02 14:59:21 +020085
86/*
87 * Memory Controller Options 0
88 */
89#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
90#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
91#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
92#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
93#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
94#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
95#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
96#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
97#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
98#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
99#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
100#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
101
102/*
103 * Memory Controller Options 1
104 */
105#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
106#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
107
108/*
109 * SDRAM DEVPOT Options
110 */
111#define SDRAM_DEVOPT_DLL 0x80000000
112#define SDRAM_DEVOPT_DS 0x40000000
113
114/*
115 * SDRAM MCSTS Options
116 */
117#define SDRAM_MCSTS_MRSC 0x80000000
118#define SDRAM_MCSTS_SRMS 0x40000000
119#define SDRAM_MCSTS_CIS 0x20000000
Stefan Roesefb951692009-09-28 17:33:45 +0200120#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */
Stefan Roese17ceb062008-06-02 14:59:21 +0200121
122/*
123 * SDRAM Refresh Timer Register
124 */
125#define SDRAM_RTR_RINT_MASK 0xFFFF0000
126#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
127
128/*
129 * SDRAM UABus Base Address Reg
130 */
131#define SDRAM_UABBA_UBBA_MASK 0x0000000F
132
133/*
134 * Memory Bank 0-7 configuration
135 */
136#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
137#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
138#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
139#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
140#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
141#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
142#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
143#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
144#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
145#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
146#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
147#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
148#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
149#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
150#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
151
152/*
153 * SDRAM TR0 Options
154 */
155#define SDRAM_TR0_SDWR_MASK 0x80000000
156#define SDRAM_TR0_SDWR_2_CLK 0x00000000
157#define SDRAM_TR0_SDWR_3_CLK 0x80000000
158#define SDRAM_TR0_SDWD_MASK 0x40000000
159#define SDRAM_TR0_SDWD_0_CLK 0x00000000
160#define SDRAM_TR0_SDWD_1_CLK 0x40000000
161#define SDRAM_TR0_SDCL_MASK 0x01800000
162#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
163#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
164#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
165#define SDRAM_TR0_SDPA_MASK 0x000C0000
166#define SDRAM_TR0_SDPA_2_CLK 0x00040000
167#define SDRAM_TR0_SDPA_3_CLK 0x00080000
168#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
169#define SDRAM_TR0_SDCP_MASK 0x00030000
170#define SDRAM_TR0_SDCP_2_CLK 0x00000000
171#define SDRAM_TR0_SDCP_3_CLK 0x00010000
172#define SDRAM_TR0_SDCP_4_CLK 0x00020000
173#define SDRAM_TR0_SDCP_5_CLK 0x00030000
174#define SDRAM_TR0_SDLD_MASK 0x0000C000
175#define SDRAM_TR0_SDLD_1_CLK 0x00000000
176#define SDRAM_TR0_SDLD_2_CLK 0x00004000
177#define SDRAM_TR0_SDRA_MASK 0x0000001C
178#define SDRAM_TR0_SDRA_6_CLK 0x00000000
179#define SDRAM_TR0_SDRA_7_CLK 0x00000004
180#define SDRAM_TR0_SDRA_8_CLK 0x00000008
181#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
182#define SDRAM_TR0_SDRA_10_CLK 0x00000010
183#define SDRAM_TR0_SDRA_11_CLK 0x00000014
184#define SDRAM_TR0_SDRA_12_CLK 0x00000018
185#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
186#define SDRAM_TR0_SDRD_MASK 0x00000003
187#define SDRAM_TR0_SDRD_2_CLK 0x00000001
188#define SDRAM_TR0_SDRD_3_CLK 0x00000002
189#define SDRAM_TR0_SDRD_4_CLK 0x00000003
190
191/*
192 * SDRAM TR1 Options
193 */
194#define SDRAM_TR1_RDSS_MASK 0xC0000000
195#define SDRAM_TR1_RDSS_TR0 0x00000000
196#define SDRAM_TR1_RDSS_TR1 0x40000000
197#define SDRAM_TR1_RDSS_TR2 0x80000000
198#define SDRAM_TR1_RDSS_TR3 0xC0000000
199#define SDRAM_TR1_RDSL_MASK 0x00C00000
200#define SDRAM_TR1_RDSL_STAGE1 0x00000000
201#define SDRAM_TR1_RDSL_STAGE2 0x00400000
202#define SDRAM_TR1_RDSL_STAGE3 0x00800000
203#define SDRAM_TR1_RDCD_MASK 0x00000800
204#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
205#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
206#define SDRAM_TR1_RDCT_MASK 0x000001FF
207#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
208#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
209#define SDRAM_TR1_RDCT_MIN 0x00000000
210#define SDRAM_TR1_RDCT_MAX 0x000001FF
211
212/*
213 * SDRAM WDDCTR Options
214 */
215#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
216#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
217#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
218#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
219#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
220
221/*
222 * SDRAM CLKTR Options
223 */
224#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
225#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
226#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
227#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
228#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
229
230/*
231 * SDRAM DLYCAL Options
232 */
233#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
234#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
235#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
236
237#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */
238
239#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
240
241#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
242#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
243#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
244
Adam Grahamf6b6c452008-09-03 12:26:59 -0700245#if !defined(CONFIG_405EX)
Stefan Roese17ceb062008-06-02 14:59:21 +0200246/*
247 * Memory queue defines
248 */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700249#define SDRAMQ_DCR_BASE 0x040
Stefan Roese17ceb062008-06-02 14:59:21 +0200250
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700251#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
252#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
253#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
254#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
255#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
256#define SDRAM_CONF1HB_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */
257#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
258#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
259#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
Yuri Tikhonovbf29e0e2008-10-17 12:54:18 +0200260#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700261#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
262#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
Yuri Tikhonovbf29e0e2008-10-17 12:54:18 +0200263#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */
264#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700265
266#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
267#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
268#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
269#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
270#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
271#define SDRAM_CONF1LL_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */
272#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
273#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
274#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
Yuri Tikhonovbf29e0e2008-10-17 12:54:18 +0200275#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700276#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
277#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
Yuri Tikhonovbf29e0e2008-10-17 12:54:18 +0200278#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700279
280#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
281#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
282#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
283#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
284#define SDRAM_CONFPATHB_TPEN 0x08000000 /* Transaction Passing Enable - Bit 4 */
285
286#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
Stefan Roese17ceb062008-06-02 14:59:21 +0200287
Stefan Roese17ceb062008-06-02 14:59:21 +0200288/*
289 * Memory Bank 0-7 configuration
290 */
291#if defined(CONFIG_440SPE) || \
Feng Kan96e5fc02008-07-08 22:48:07 -0700292 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
293 defined(CONFIG_460SX)
Stefan Roese17ceb062008-06-02 14:59:21 +0200294#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
Stefan Roese5d812b82008-07-09 17:33:57 +0200295#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
296#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
Stefan Roese17ceb062008-06-02 14:59:21 +0200297#endif /* CONFIG_440SPE */
298#if defined(CONFIG_440SP)
299#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
300#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFF800000))
301#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFF800000))
302#endif /* CONFIG_440SP */
303#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
304#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((u32)(n))&0x3FF)<<6)
305#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((u32)(n))>>6)&0x3FF)
306#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
307#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
308#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
309#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
310#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
311#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
312#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
313#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
314#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
315#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
316#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
317#else /* CONFIG_405EX */
318/*
319 * XXX - ToDo:
320 * Revisit this file to check if all these 405EX defines are correct and
321 * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02
322 */
323#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF)
324#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0)
325#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1)
326#define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2)
327#define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3)
328#define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4)
329#define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5)
330#define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6)
331#define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7)
332#define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8)
333#define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9)
334#define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA)
335#define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB)
336#define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB
337#define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB
338#define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB
339#define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB
340#define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB
341#define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB
342#define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB
343#define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB
344#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB
345#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB
346#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB
347#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0)
348#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1)
349#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2)
350#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3)
351#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4)
352#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5)
353#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6)
354#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7)
355#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8)
356#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9)
357#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0)
358#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1)
359#endif /* CONFIG_405EX */
360
361/*
362 * Memory controller registers
363 */
Grant Ericksonad7382d2008-07-09 16:31:59 -0700364#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
365#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
366#define SDRAM_BEARL 0x02 /* PLB bus error address low */
367#define SDRAM_BEARH 0x03 /* PLB bus error address high */
368#define SDRAM_WMIRQ 0x06 /* PLB write master interrupt (read/clear) */
369#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */
370#define SDRAM_PLBOPT 0x08 /* PLB slave options */
371#define SDRAM_PUABA 0x09 /* PLB upper address base */
Grant Erickson5b457d02008-07-09 11:55:46 -0700372#ifndef CONFIG_405EX
Stefan Roese17ceb062008-06-02 14:59:21 +0200373#define SDRAM_MCSTAT 0x14 /* memory controller status */
Grant Erickson5b457d02008-07-09 11:55:46 -0700374#else
375#define SDRAM_MCSTAT 0x1F /* memory controller status */
376#endif
Stefan Roese17ceb062008-06-02 14:59:21 +0200377#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
378#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
379#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
380#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
381#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
382#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
383#define SDRAM_CODT 0x26 /* on die termination for controller */
384#define SDRAM_VVPR 0x27 /* variable VRef programmming */
385#define SDRAM_OPARS 0x28 /* on chip driver control setup */
386#define SDRAM_OPART 0x29 /* on chip driver control trigger */
387#define SDRAM_RTR 0x30 /* refresh timer */
388#define SDRAM_PMIT 0x34 /* power management idle timer */
389#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
390#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
391#define SDRAM_MB2CF 0x48
392#define SDRAM_MB3CF 0x4C
393#define SDRAM_INITPLR0 0x50 /* manual initialization control */
394#define SDRAM_INITPLR1 0x51 /* manual initialization control */
395#define SDRAM_INITPLR2 0x52 /* manual initialization control */
396#define SDRAM_INITPLR3 0x53 /* manual initialization control */
397#define SDRAM_INITPLR4 0x54 /* manual initialization control */
398#define SDRAM_INITPLR5 0x55 /* manual initialization control */
399#define SDRAM_INITPLR6 0x56 /* manual initialization control */
400#define SDRAM_INITPLR7 0x57 /* manual initialization control */
401#define SDRAM_INITPLR8 0x58 /* manual initialization control */
402#define SDRAM_INITPLR9 0x59 /* manual initialization control */
403#define SDRAM_INITPLR10 0x5a /* manual initialization control */
404#define SDRAM_INITPLR11 0x5b /* manual initialization control */
405#define SDRAM_INITPLR12 0x5c /* manual initialization control */
406#define SDRAM_INITPLR13 0x5d /* manual initialization control */
407#define SDRAM_INITPLR14 0x5e /* manual initialization control */
408#define SDRAM_INITPLR15 0x5f /* manual initialization control */
409#define SDRAM_RQDC 0x70 /* read DQS delay control */
410#define SDRAM_RFDC 0x74 /* read feedback delay control */
411#define SDRAM_RDCC 0x78 /* read data capture control */
412#define SDRAM_DLCR 0x7A /* delay line calibration */
413#define SDRAM_CLKTR 0x80 /* DDR clock timing */
414#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
415#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
416#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
417#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
418#define SDRAM_MMODE 0x88 /* memory mode */
419#define SDRAM_MEMODE 0x89 /* memory extended mode */
Stefan Roesefb951692009-09-28 17:33:45 +0200420#define SDRAM_ECCES 0x98 /* ECC error status */
Stefan Roese17ceb062008-06-02 14:59:21 +0200421#define SDRAM_CID 0xA4 /* core ID */
Grant Ericksonad7382d2008-07-09 16:31:59 -0700422#ifndef CONFIG_405EX
Stefan Roese17ceb062008-06-02 14:59:21 +0200423#define SDRAM_RID 0xA8 /* revision ID */
Grant Ericksonad7382d2008-07-09 16:31:59 -0700424#endif
425#define SDRAM_FCSR 0xB0 /* feedback calibration status */
Stefan Roese17ceb062008-06-02 14:59:21 +0200426#define SDRAM_RTSR 0xB1 /* run time status tracking */
Grant Ericksonad7382d2008-07-09 16:31:59 -0700427#ifdef CONFIG_405EX
428#define SDRAM_RID 0xF8 /* revision ID */
429#endif
430
431/*
432 * Memory Controller Bus Error Status
433 */
434#define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF)
435#define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF)
436#define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, 0x0)
437#define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, 0x1)
438#define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, 0x2)
439#define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, 0x3)
440#define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, 0x4)
441#define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, 0x5)
442#define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, 0x6)
443#define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, 0x7)
444#define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7)
445#define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0x0)
446#define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 0x1)
447#define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0)
448#define SDRAM_BESR_M0RW_READ PPC_REG_VAL(8, 1)
Stefan Roese17ceb062008-06-02 14:59:21 +0200449
450/*
451 * Memory Controller Status
452 */
453#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
454#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
455#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
456#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
457#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
458#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
459#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
460#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
461#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
462
463/*
464 * Memory Controller Options 1
465 */
466#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
467#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
468#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
469#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
470#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
471#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((u32)(n))>>28)&0x3)
472#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
473#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
474#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
475#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
476#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
477#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
478#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
479#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
480#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
481#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
482#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
483#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
484#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
485#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
486#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
487#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
488#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
489#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
490#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
491#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
492#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
493#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
494#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
495#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
496#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
497#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
498#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
499#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
500#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
501
502/*
503 * Memory Controller Options 2
504 */
505#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
506#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
507#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
508#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
509#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
510#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
511#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
512#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
513#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
514#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
515#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
516#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
517#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
518#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
519#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
520#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
521#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
522#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
523
524/*
525 * SDRAM Refresh Timer Register
526 */
527#define SDRAM_RTR_RINT_MASK 0xFFF80000
528#define SDRAM_RTR_RINT_ENCODE(n) ((((u32)(n))&0xFFF8)<<16)
529#define SDRAM_RTR_RINT_DECODE(n) ((((u32)(n))>>16)&0xFFF8)
530
531/*
532 * SDRAM Read DQS Delay Control Register
533 */
534#define SDRAM_RQDC_RQDE_MASK 0x80000000
535#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
536#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
537#define SDRAM_RQDC_RQFD_MASK 0x000001FF
538#define SDRAM_RQDC_RQFD_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
539
540#define SDRAM_RQDC_RQFD_MAX 0x1FF
541
542/*
543 * SDRAM Read Data Capture Control Register
544 */
545#define SDRAM_RDCC_RDSS_MASK 0xC0000000
546#define SDRAM_RDCC_RDSS_T1 0x00000000
547#define SDRAM_RDCC_RDSS_T2 0x40000000
548#define SDRAM_RDCC_RDSS_T3 0x80000000
549#define SDRAM_RDCC_RDSS_T4 0xC0000000
550#define SDRAM_RDCC_RSAE_MASK 0x00000001
551#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
552#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
Adam Grahamc6450122009-02-09 13:18:12 -0800553#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30)
554#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03)
Stefan Roese17ceb062008-06-02 14:59:21 +0200555
556/*
557 * SDRAM Read Feedback Delay Control Register
558 */
559#define SDRAM_RFDC_ARSE_MASK 0x80000000
560#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
561#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
562#define SDRAM_RFDC_RFOS_MASK 0x007F0000
563#define SDRAM_RFDC_RFOS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
564#define SDRAM_RFDC_RFFD_MASK 0x000007FF
565#define SDRAM_RFDC_RFFD_ENCODE(n) ((((u32)(n))&0x7FF)<<0)
566
567#define SDRAM_RFDC_RFFD_MAX 0x7FF
568
569/*
570 * SDRAM Delay Line Calibration Register
571 */
572#define SDRAM_DLCR_DCLM_MASK 0x80000000
Grant Erickson2e205082008-07-09 16:46:35 -0700573#define SDRAM_DLCR_DCLM_MANUAL 0x80000000
Stefan Roese17ceb062008-06-02 14:59:21 +0200574#define SDRAM_DLCR_DCLM_AUTO 0x00000000
575#define SDRAM_DLCR_DLCR_MASK 0x08000000
576#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
577#define SDRAM_DLCR_DLCR_IDLE 0x00000000
578#define SDRAM_DLCR_DLCS_MASK 0x07000000
579#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
580#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
581#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
582#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
583#define SDRAM_DLCR_DLCS_ERROR 0x04000000
584#define SDRAM_DLCR_DLCV_MASK 0x000001FF
585#define SDRAM_DLCR_DLCV_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
586#define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF)
587
588/*
Grant Erickson2e205082008-07-09 16:46:35 -0700589 * SDRAM Memory On Die Terimination Control Register
590 */
591#define SDRAM_MODT_ODTON_DISABLE PPC_REG_VAL(0, 0)
592#define SDRAM_MODT_ODTON_ENABLE PPC_REG_VAL(0, 1)
593#define SDRAM_MODT_EB1W_DISABLE PPC_REG_VAL(1, 0)
594#define SDRAM_MODT_EB1W_ENABLE PPC_REG_VAL(1, 1)
595#define SDRAM_MODT_EB1R_DISABLE PPC_REG_VAL(2, 0)
596#define SDRAM_MODT_EB1R_ENABLE PPC_REG_VAL(2, 1)
597#define SDRAM_MODT_EB0W_DISABLE PPC_REG_VAL(7, 0)
598#define SDRAM_MODT_EB0W_ENABLE PPC_REG_VAL(7, 1)
599#define SDRAM_MODT_EB0R_DISABLE PPC_REG_VAL(8, 0)
600#define SDRAM_MODT_EB0R_ENABLE PPC_REG_VAL(8, 1)
601
602/*
Stefan Roese17ceb062008-06-02 14:59:21 +0200603 * SDRAM Controller On Die Termination Register
604 */
Grant Erickson2e205082008-07-09 16:46:35 -0700605#define SDRAM_CODT_ODT_ON PPC_REG_VAL(0, 1)
606#define SDRAM_CODT_ODT_OFF PPC_REG_VAL(0, 0)
607#define SDRAM_CODT_RK1W_ON PPC_REG_VAL(1, 1)
608#define SDRAM_CODT_RK1W_OFF PPC_REG_VAL(1, 0)
609#define SDRAM_CODT_RK1R_ON PPC_REG_VAL(2, 1)
610#define SDRAM_CODT_RK1R_OFF PPC_REG_VAL(2, 0)
611#define SDRAM_CODT_RK0W_ON PPC_REG_VAL(7, 1)
612#define SDRAM_CODT_RK0W_OFF PPC_REG_VAL(7, 0)
613#define SDRAM_CODT_RK0R_ON PPC_REG_VAL(8, 1)
614#define SDRAM_CODT_RK0R_OFF PPC_REG_VAL(8, 0)
615#define SDRAM_CODT_ODTSH_NORMAL PPC_REG_VAL(10, 0)
616#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END PPC_REG_VAL(10, 1)
617#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START PPC_REG_VAL(10, 2)
618#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER PPC_REG_VAL(10, 3)
619#define SDRAM_CODT_CODTZ_75OHM PPC_REG_VAL(11, 0)
620#define SDRAM_CODT_CKEG_ON PPC_REG_VAL(12, 1)
621#define SDRAM_CODT_CKEG_OFF PPC_REG_VAL(12, 0)
622#define SDRAM_CODT_CTLG_ON PPC_REG_VAL(13, 1)
623#define SDRAM_CODT_CTLG_OFF PPC_REG_VAL(13, 0)
624#define SDRAM_CODT_FBDG_ON PPC_REG_VAL(14, 1)
625#define SDRAM_CODT_FBDG_OFF PPC_REG_VAL(14, 0)
626#define SDRAM_CODT_FBRG_ON PPC_REG_VAL(15, 1)
627#define SDRAM_CODT_FBRG_OFF PPC_REG_VAL(15, 0)
628#define SDRAM_CODT_CKLZ_36OHM PPC_REG_VAL(18, 1)
629#define SDRAM_CODT_CKLZ_18OHM PPC_REG_VAL(18, 0)
630#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK PPC_REG_VAL(26, 1)
631#define SDRAM_CODT_DQS_2_5_V_DDR1 PPC_REG_VAL(26, 0)
632#define SDRAM_CODT_DQS_1_8_V_DDR2 PPC_REG_VAL(26, 1)
633#define SDRAM_CODT_DQS_MASK PPC_REG_VAL(27, 1)
634#define SDRAM_CODT_DQS_DIFFERENTIAL PPC_REG_VAL(27, 0)
635#define SDRAM_CODT_DQS_SINGLE_END PPC_REG_VAL(27, 1)
636#define SDRAM_CODT_CKSE_DIFFERENTIAL PPC_REG_VAL(28, 0)
637#define SDRAM_CODT_CKSE_SINGLE_END PPC_REG_VAL(28, 1)
638#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END PPC_REG_VAL(29, 1)
639#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END PPC_REG_VAL(30, 1)
640#define SDRAM_CODT_IO_HIZ PPC_REG_VAL(31, 0)
641#define SDRAM_CODT_IO_NMODE PPC_REG_VAL(31, 1)
Stefan Roese17ceb062008-06-02 14:59:21 +0200642
643/*
Grant Erickson2e205082008-07-09 16:46:35 -0700644 * SDRAM Initialization Preload Register
Stefan Roese17ceb062008-06-02 14:59:21 +0200645 */
Grant Erickson2e205082008-07-09 16:46:35 -0700646#define SDRAM_INITPLR_ENABLE PPC_REG_VAL(0, 1)
647#define SDRAM_INITPLR_DISABLE PPC_REG_VAL(0, 0)
648#define SDRAM_INITPLR_IMWT_MASK PPC_REG_VAL(8, 0xFF)
649#define SDRAM_INITPLR_IMWT_ENCODE(n) PPC_REG_VAL(8, \
650 (static_cast(u32, \
651 n)) \
652 & 0xFF)
653#define SDRAM_INITPLR_ICMD_MASK PPC_REG_VAL(12, 0x7)
654#define SDRAM_INITPLR_ICMD_ENCODE(n) PPC_REG_VAL(12, \
655 (static_cast(u32, \
656 n)) \
657 & 0x7)
658#define SDRAM_INITPLR_IBA_MASK PPC_REG_VAL(15, 0x7)
659#define SDRAM_INITPLR_IBA_ENCODE(n) PPC_REG_VAL(15, \
660 (static_cast(u32, \
661 n)) \
662 & 0x7)
663#define SDRAM_INITPLR_IMA_MASK PPC_REG_VAL(31, 0x7FFF)
664#define SDRAM_INITPLR_IMA_ENCODE(n) PPC_REG_VAL(31, \
665 (static_cast(u32, \
666 n)) \
667 & 0x7FFF)
Stefan Roese17ceb062008-06-02 14:59:21 +0200668
669/*
Grant Erickson2e205082008-07-09 16:46:35 -0700670 * JEDEC DDR Initialization Commands
Stefan Roese17ceb062008-06-02 14:59:21 +0200671 */
Grant Erickson2e205082008-07-09 16:46:35 -0700672#define JEDEC_CMD_NOP 7
673#define JEDEC_CMD_PRECHARGE 2
674#define JEDEC_CMD_REFRESH 1
675#define JEDEC_CMD_EMR 0
676#define JEDEC_CMD_READ 5
677#define JEDEC_CMD_WRITE 4
678
679/*
680 * JEDEC Precharge Command Memory Address Arguments
681 */
682#define JEDEC_MA_PRECHARGE_ONE (0 << 10)
683#define JEDEC_MA_PRECHARGE_ALL (1 << 10)
684
685/*
686 * JEDEC DDR EMR Command Bank Address Arguments
687 */
688#define JEDEC_BA_MR 0
689#define JEDEC_BA_EMR 1
690#define JEDEC_BA_EMR2 2
691#define JEDEC_BA_EMR3 3
692
693/*
694 * JEDEC DDR Mode Register
695 */
696#define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12)
697#define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12)
698#define JEDEC_MA_MR_WR_MASK (0x7 << 9)
699#define JEDEC_MA_MR_WR_DDR1 (0x0 << 9)
700#define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9)
701#define JEDEC_MA_MR_WR_DDR2_3_CYC (0x2 << 9)
702#define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9)
703#define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9)
704#define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9)
705#define JEDEC_MA_MR_DLL_RESET (1 << 8)
706#define JEDEC_MA_MR_MODE_NORMAL (0 << 8)
707#define JEDEC_MA_MR_MODE_TEST (1 << 8)
708#define JEDEC_MA_MR_CL_MASK (0x7 << 4)
709#define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4)
710#define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4)
711#define JEDEC_MA_MR_CL_DDR1_3_0_CLK (0x3 << 4)
712#define JEDEC_MA_MR_CL_DDR2_2_0_CLK (0x2 << 4)
713#define JEDEC_MA_MR_CL_DDR2_3_0_CLK (0x3 << 4)
714#define JEDEC_MA_MR_CL_DDR2_4_0_CLK (0x4 << 4)
715#define JEDEC_MA_MR_CL_DDR2_5_0_CLK (0x5 << 4)
716#define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4)
717#define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4)
718#define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3)
719#define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3)
720#define JEDEC_MA_MR_BLEN_MASK (0x7 << 0)
721#define JEDEC_MA_MR_BLEN_4 (2 << 0)
722#define JEDEC_MA_MR_BLEN_8 (3 << 0)
723
724/*
725 * JEDEC DDR Extended Mode Register
726 */
727#define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12)
728#define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12)
729#define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12)
730#define JEDEC_MA_EMR_RQDS_MASK (1 << 11)
731#define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11)
732#define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11)
733#define JEDEC_MA_EMR_DQS_MASK (1 << 10)
734#define JEDEC_MA_EMR_DQS_DISABLE (1 << 10)
735#define JEDEC_MA_EMR_DQS_ENABLE (0 << 10)
736#define JEDEC_MA_EMR_OCD_MASK (0x7 << 7)
737#define JEDEC_MA_EMR_OCD_EXIT (0 << 7)
738#define JEDEC_MA_EMR_OCD_ENTER (7 << 7)
739#define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3)
740#define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3)
741#define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3)
742#define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3)
743#define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3)
744#define JEDEC_MA_EMR_RTT_MASK (0x11 << 2)
745#define JEDEC_MA_EMR_RTT_DISABLED (0x00 << 2)
746#define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2)
747#define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2)
748#define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2)
749#define JEDEC_MA_EMR_ODS_MASK (1 << 1)
750#define JEDEC_MA_EMR_ODS_NORMAL (0 << 1)
751#define JEDEC_MA_EMR_ODS_WEAK (1 << 1)
752#define JEDEC_MA_EMR_DLL_MASK (1 << 0)
753#define JEDEC_MA_EMR_DLL_ENABLE (0 << 0)
754#define JEDEC_MA_EMR_DLL_DISABLE (1 << 0)
755
756/*
757 * JEDEC DDR Extended Mode Register 2
758 */
759#define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7)
760#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7)
761
762/*
763 * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register)
764 */
765#define SDRAM_MMODE_WR_MASK JEDEC_MA_MR_WR_MASK
766#define SDRAM_MMODE_WR_DDR1 JEDEC_MA_MR_WR_DDR1
767#define SDRAM_MMODE_WR_DDR2_2_CYC JEDEC_MA_MR_WR_DDR2_2_CYC
768#define SDRAM_MMODE_WR_DDR2_3_CYC JEDEC_MA_MR_WR_DDR2_3_CYC
769#define SDRAM_MMODE_WR_DDR2_4_CYC JEDEC_MA_MR_WR_DDR2_4_CYC
770#define SDRAM_MMODE_WR_DDR2_5_CYC JEDEC_MA_MR_WR_DDR2_5_CYC
771#define SDRAM_MMODE_WR_DDR2_6_CYC JEDEC_MA_MR_WR_DDR2_6_CYC
772#define SDRAM_MMODE_DCL_MASK JEDEC_MA_MR_CL_MASK
773#define SDRAM_MMODE_DCL_DDR1_2_0_CLK JEDEC_MA_MR_CL_DDR1_2_0_CLK
774#define SDRAM_MMODE_DCL_DDR1_2_5_CLK JEDEC_MA_MR_CL_DDR1_2_5_CLK
775#define SDRAM_MMODE_DCL_DDR1_3_0_CLK JEDEC_MA_MR_CL_DDR1_3_0_CLK
776#define SDRAM_MMODE_DCL_DDR2_2_0_CLK JEDEC_MA_MR_CL_DDR2_2_0_CLK
777#define SDRAM_MMODE_DCL_DDR2_3_0_CLK JEDEC_MA_MR_CL_DDR2_3_0_CLK
778#define SDRAM_MMODE_DCL_DDR2_4_0_CLK JEDEC_MA_MR_CL_DDR2_4_0_CLK
779#define SDRAM_MMODE_DCL_DDR2_5_0_CLK JEDEC_MA_MR_CL_DDR2_5_0_CLK
780#define SDRAM_MMODE_DCL_DDR2_6_0_CLK JEDEC_MA_MR_CL_DDR2_6_0_CLK
781#define SDRAM_MMODE_DCL_DDR2_7_0_CLK JEDEC_MA_MR_CL_DDR2_7_0_CLK
782#define SDRAM_MMODE_BTYP_SEQUENTIAL JEDEC_MA_MR_BTYP_SEQUENTIAL
783#define SDRAM_MMODE_BTYP_INTERLEAVED JEDEC_MA_MR_BTYP_INTERLEAVED
784#define SDRAM_MMODE_BLEN_MASK JEDEC_MA_MR_BLEN_MASK
785#define SDRAM_MMODE_BLEN_4 JEDEC_MA_MR_BLEN_4
786#define SDRAM_MMODE_BLEN_8 JEDEC_MA_MR_BLEN_8
787
788/*
789 * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended
790 * Mode Register)
791 */
792#define SDRAM_MEMODE_QOFF_MASK JEDEC_MA_EMR_OUTPUT_MASK
793#define SDRAM_MEMODE_QOFF_DISABLE JEDEC_MA_EMR_OUTPUT_DISABLE
794#define SDRAM_MEMODE_QOFF_ENABLE JEDEC_MA_EMR_OUTPUT_ENABLE
795#define SDRAM_MEMODE_RDQS_MASK JEDEC_MA_EMR_RQDS_MASK
796#define SDRAM_MEMODE_RDQS_DISABLE JEDEC_MA_EMR_RDQS_DISABLE
797#define SDRAM_MEMODE_RDQS_ENABLE JEDEC_MA_EMR_RDQS_ENABLE
798#define SDRAM_MEMODE_DQS_MASK JEDEC_MA_EMR_DQS_MASK
799#define SDRAM_MEMODE_DQS_DISABLE JEDEC_MA_EMR_DQS_DISABLE
800#define SDRAM_MEMODE_DQS_ENABLE JEDEC_MA_EMR_DQS_ENABLE
801#define SDRAM_MEMODE_AL_DDR1_0_CYC JEDEC_MA_EMR_AL_DDR1_0_CYC
802#define SDRAM_MEMODE_AL_DDR2_1_CYC JEDEC_MA_EMR_AL_DDR2_1_CYC
803#define SDRAM_MEMODE_AL_DDR2_2_CYC JEDEC_MA_EMR_AL_DDR2_2_CYC
804#define SDRAM_MEMODE_AL_DDR2_3_CYC JEDEC_MA_EMR_AL_DDR2_3_CYC
805#define SDRAM_MEMODE_AL_DDR2_4_CYC JEDEC_MA_EMR_AL_DDR2_4_CYC
806#define SDRAM_MEMODE_RTT_MASK JEDEC_MA_EMR_RTT_MASK
807#define SDRAM_MEMODE_RTT_DISABLED JEDEC_MA_EMR_RTT_DISABLED
808#define SDRAM_MEMODE_RTT_75OHM JEDEC_MA_EMR_RTT_75OHM
809#define SDRAM_MEMODE_RTT_150OHM JEDEC_MA_EMR_RTT_150OHM
810#define SDRAM_MEMODE_RTT_50OHM JEDEC_MA_EMR_RTT_50OHM
811#define SDRAM_MEMODE_DIC_MASK JEDEC_MA_EMR_ODS_MASK
812#define SDRAM_MEMODE_DIC_NORMAL JEDEC_MA_EMR_ODS_NORMAL
813#define SDRAM_MEMODE_DIC_WEAK JEDEC_MA_EMR_ODS_WEAK
814#define SDRAM_MEMODE_DLL_MASK JEDEC_MA_EMR_DLL_MASK
815#define SDRAM_MEMODE_DLL_DISABLE JEDEC_MA_EMR_DLL_DISABLE
816#define SDRAM_MEMODE_DLL_ENABLE JEDEC_MA_EMR_DLL_ENABLE
Stefan Roese17ceb062008-06-02 14:59:21 +0200817
818/*
819 * SDRAM Clock Timing Register
820 */
821#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
822#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
823#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
824#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000
825#define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000
826
827/*
828 * SDRAM Write Timing Register
829 */
830#define SDRAM_WRDTR_LLWP_MASK 0x10000000
831#define SDRAM_WRDTR_LLWP_DIS 0x10000000
832#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
833#define SDRAM_WRDTR_WTR_MASK 0x0E000000
834#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
835#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
836#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
837#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
838
839/*
840 * SDRAM SDTR1 Options
841 */
842#define SDRAM_SDTR1_LDOF_MASK 0x80000000
843#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
844#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
845#define SDRAM_SDTR1_RTW_MASK 0x00F00000
846#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
847#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
848#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
849#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
850#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
851#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
852#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
853#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
854
855/*
856 * SDRAM SDTR2 Options
857 */
858#define SDRAM_SDTR2_RCD_MASK 0xF0000000
859#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
860#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
861#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
862#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
863#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
864#define SDRAM_SDTR2_WTR_MASK 0x0F000000
865#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
866#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
867#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
868#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
869#define SDRAM_SDTR3_WTR_ENCODE(n) ((((u32)(n))&0xF)<<24)
870#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
871#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
872#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
873#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
874#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
875#define SDRAM_SDTR2_WPC_MASK 0x0000F000
876#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
877#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
878#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
879#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
880#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
881#define SDRAM_SDTR3_WPC_ENCODE(n) ((((u32)(n))&0xF)<<12)
882#define SDRAM_SDTR2_RPC_MASK 0x00000F00
883#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
884#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
885#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
886#define SDRAM_SDTR2_RP_MASK 0x000000F0
887#define SDRAM_SDTR2_RP_3_CLK 0x00000030
888#define SDRAM_SDTR2_RP_4_CLK 0x00000040
889#define SDRAM_SDTR2_RP_5_CLK 0x00000050
890#define SDRAM_SDTR2_RP_6_CLK 0x00000060
891#define SDRAM_SDTR2_RP_7_CLK 0x00000070
892#define SDRAM_SDTR2_RRD_MASK 0x0000000F
893#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
894#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
895
896/*
897 * SDRAM SDTR3 Options
898 */
899#define SDRAM_SDTR3_RAS_MASK 0x1F000000
900#define SDRAM_SDTR3_RAS_ENCODE(n) ((((u32)(n))&0x1F)<<24)
901#define SDRAM_SDTR3_RC_MASK 0x001F0000
902#define SDRAM_SDTR3_RC_ENCODE(n) ((((u32)(n))&0x1F)<<16)
903#define SDRAM_SDTR3_XCS_MASK 0x00001F00
904#define SDRAM_SDTR3_XCS 0x00000D00
905#define SDRAM_SDTR3_RFC_MASK 0x0000003F
906#define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0)
907
908/*
Grant Ericksonad7382d2008-07-09 16:31:59 -0700909 * ECC Error Status
910 */
911#define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF)
912#define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF)
913#define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1)
914#define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3)
915#define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0)
916#define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2)
917#define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1)
918#define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2)
919#define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3)
920#define SDRAM_ECCES_CE PPC_REG_VAL(18, 1)
921#define SDRAM_ECCES_UE PPC_REG_VAL(19, 1)
922#define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3)
923#define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1)
924#define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1)
925
926/*
Stefan Roese17ceb062008-06-02 14:59:21 +0200927 * Memory Bank 0-1 configuration
928 */
929#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
930#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
931#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
932#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
933#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
934#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
935#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
936#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
937#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
938#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
939#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
940#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
941#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
942#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
943
944#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/
945#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */
946#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */
947#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */
948#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */
949
950#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */
951
952#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
953
954#if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
955/*
956 * SDRAM Controller
957 */
958#define DDR0_00 0x00
959#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
960#define DDR0_00_INT_ACK_ALL 0x7F000000
961#define DDR0_00_INT_ACK_ENCODE(n) ((((u32)(n))&0x7F)<<24)
962#define DDR0_00_INT_ACK_DECODE(n) ((((u32)(n))>>24)&0x7F)
963/* Status */
964#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
965/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
966#define DDR0_00_INT_STATUS_BIT0 0x00010000
967/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
968#define DDR0_00_INT_STATUS_BIT1 0x00020000
969/* Bit2. Single correctable ECC event detected */
970#define DDR0_00_INT_STATUS_BIT2 0x00040000
971/* Bit3. Multiple correctable ECC events detected. */
972#define DDR0_00_INT_STATUS_BIT3 0x00080000
973/* Bit4. Single uncorrectable ECC event detected. */
974#define DDR0_00_INT_STATUS_BIT4 0x00100000
975/* Bit5. Multiple uncorrectable ECC events detected. */
976#define DDR0_00_INT_STATUS_BIT5 0x00200000
977/* Bit6. DRAM initialization complete. */
978#define DDR0_00_INT_STATUS_BIT6 0x00400000
979/* Bit7. Logical OR of all lower bits. */
980#define DDR0_00_INT_STATUS_BIT7 0x00800000
981
982#define DDR0_00_INT_STATUS_ENCODE(n) ((((u32)(n))&0xFF)<<16)
983#define DDR0_00_INT_STATUS_DECODE(n) ((((u32)(n))>>16)&0xFF)
984#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
985#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
986#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((u32)(n))>>8)&0x7F)
987#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
988#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
989#define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F)
990
991#define DDR0_01 0x01
992#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
993#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24)
994#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F)
995#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
996#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16)
997#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F)
998#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
999#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8)
1000#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7)
1001#define DDR0_01_INT_MASK_MASK 0x000000FF
1002#define DDR0_01_INT_MASK_ENCODE(n) ((((u32)(n))&0xFF)<<0)
1003#define DDR0_01_INT_MASK_DECODE(n) ((((u32)(n))>>0)&0xFF)
1004#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
1005#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
1006
1007#define DDR0_02 0x02
1008#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
1009#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((u32)(n))&0x2)<<24)
1010#define DDR0_02_MAX_CS_REG_DECODE(n) ((((u32)(n))>>24)&0x2)
1011#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
1012#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((u32)(n))&0xF)<<16)
1013#define DDR0_02_MAX_COL_REG_DECODE(n) ((((u32)(n))>>16)&0xF)
1014#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
1015#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((u32)(n))&0xF)<<8)
1016#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((u32)(n))>>8)&0xF)
1017#define DDR0_02_START_MASK 0x00000001
1018#define DDR0_02_START_ENCODE(n) ((((u32)(n))&0x1)<<0)
1019#define DDR0_02_START_DECODE(n) ((((u32)(n))>>0)&0x1)
1020#define DDR0_02_START_OFF 0x00000000
1021#define DDR0_02_START_ON 0x00000001
1022
1023#define DDR0_03 0x03
1024#define DDR0_03_BSTLEN_MASK 0x07000000
1025#define DDR0_03_BSTLEN_ENCODE(n) ((((u32)(n))&0x7)<<24)
1026#define DDR0_03_BSTLEN_DECODE(n) ((((u32)(n))>>24)&0x7)
1027#define DDR0_03_CASLAT_MASK 0x00070000
1028#define DDR0_03_CASLAT_ENCODE(n) ((((u32)(n))&0x7)<<16)
1029#define DDR0_03_CASLAT_DECODE(n) ((((u32)(n))>>16)&0x7)
1030#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
1031#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((u32)(n))&0xF)<<8)
1032#define DDR0_03_CASLAT_LIN_DECODE(n) ((((u32)(n))>>8)&0xF)
1033#define DDR0_03_INITAREF_MASK 0x0000000F
1034#define DDR0_03_INITAREF_ENCODE(n) ((((u32)(n))&0xF)<<0)
1035#define DDR0_03_INITAREF_DECODE(n) ((((u32)(n))>>0)&0xF)
1036
1037#define DDR0_04 0x04
1038#define DDR0_04_TRC_MASK 0x1F000000
1039#define DDR0_04_TRC_ENCODE(n) ((((u32)(n))&0x1F)<<24)
1040#define DDR0_04_TRC_DECODE(n) ((((u32)(n))>>24)&0x1F)
1041#define DDR0_04_TRRD_MASK 0x00070000
1042#define DDR0_04_TRRD_ENCODE(n) ((((u32)(n))&0x7)<<16)
1043#define DDR0_04_TRRD_DECODE(n) ((((u32)(n))>>16)&0x7)
1044#define DDR0_04_TRTP_MASK 0x00000700
1045#define DDR0_04_TRTP_ENCODE(n) ((((u32)(n))&0x7)<<8)
1046#define DDR0_04_TRTP_DECODE(n) ((((u32)(n))>>8)&0x7)
1047
1048#define DDR0_05 0x05
1049#define DDR0_05_TMRD_MASK 0x1F000000
1050#define DDR0_05_TMRD_ENCODE(n) ((((u32)(n))&0x1F)<<24)
1051#define DDR0_05_TMRD_DECODE(n) ((((u32)(n))>>24)&0x1F)
1052#define DDR0_05_TEMRS_MASK 0x00070000
1053#define DDR0_05_TEMRS_ENCODE(n) ((((u32)(n))&0x7)<<16)
1054#define DDR0_05_TEMRS_DECODE(n) ((((u32)(n))>>16)&0x7)
1055#define DDR0_05_TRP_MASK 0x00000F00
1056#define DDR0_05_TRP_ENCODE(n) ((((u32)(n))&0xF)<<8)
1057#define DDR0_05_TRP_DECODE(n) ((((u32)(n))>>8)&0xF)
1058#define DDR0_05_TRAS_MIN_MASK 0x000000FF
1059#define DDR0_05_TRAS_MIN_ENCODE(n) ((((u32)(n))&0xFF)<<0)
1060#define DDR0_05_TRAS_MIN_DECODE(n) ((((u32)(n))>>0)&0xFF)
1061
1062#define DDR0_06 0x06
1063#define DDR0_06_WRITEINTERP_MASK 0x01000000
1064#define DDR0_06_WRITEINTERP_ENCODE(n) ((((u32)(n))&0x1)<<24)
1065#define DDR0_06_WRITEINTERP_DECODE(n) ((((u32)(n))>>24)&0x1)
1066#define DDR0_06_TWTR_MASK 0x00070000
1067#define DDR0_06_TWTR_ENCODE(n) ((((u32)(n))&0x7)<<16)
1068#define DDR0_06_TWTR_DECODE(n) ((((u32)(n))>>16)&0x7)
1069#define DDR0_06_TDLL_MASK 0x0000FF00
1070#define DDR0_06_TDLL_ENCODE(n) ((((u32)(n))&0xFF)<<8)
1071#define DDR0_06_TDLL_DECODE(n) ((((u32)(n))>>8)&0xFF)
1072#define DDR0_06_TRFC_MASK 0x0000007F
1073#define DDR0_06_TRFC_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1074#define DDR0_06_TRFC_DECODE(n) ((((u32)(n))>>0)&0x7F)
1075
1076#define DDR0_07 0x07
1077#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
1078#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((u32)(n))&0x1)<<24)
1079#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((u32)(n))>>24)&0x1)
1080#define DDR0_07_TFAW_MASK 0x001F0000
1081#define DDR0_07_TFAW_ENCODE(n) ((((u32)(n))&0x1F)<<16)
1082#define DDR0_07_TFAW_DECODE(n) ((((u32)(n))>>16)&0x1F)
1083#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
1084#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8)
1085#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1)
1086#define DDR0_07_AREFRESH_MASK 0x00000001
1087#define DDR0_07_AREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<0)
1088#define DDR0_07_AREFRESH_DECODE(n) ((((u32)(n))>>0)&0x1)
1089
1090#define DDR0_08 0x08
1091#define DDR0_08_WRLAT_MASK 0x07000000
1092#define DDR0_08_WRLAT_ENCODE(n) ((((u32)(n))&0x7)<<24)
1093#define DDR0_08_WRLAT_DECODE(n) ((((u32)(n))>>24)&0x7)
1094#define DDR0_08_TCPD_MASK 0x00FF0000
1095#define DDR0_08_TCPD_ENCODE(n) ((((u32)(n))&0xFF)<<16)
1096#define DDR0_08_TCPD_DECODE(n) ((((u32)(n))>>16)&0xFF)
1097#define DDR0_08_DQS_N_EN_MASK 0x00000100
1098#define DDR0_08_DQS_N_EN_ENCODE(n) ((((u32)(n))&0x1)<<8)
1099#define DDR0_08_DQS_N_EN_DECODE(n) ((((u32)(n))>>8)&0x1)
1100#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
1101#define DDR0_08_DDRII_ENCODE(n) ((((u32)(n))&0x1)<<0)
1102#define DDR0_08_DDRII_DECODE(n) ((((u32)(n))>>0)&0x1)
1103
1104#define DDR0_09 0x09
1105#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
1106#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24)
1107#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F)
1108#define DDR0_09_RTT_0_MASK 0x00030000
1109#define DDR0_09_RTT_0_ENCODE(n) ((((u32)(n))&0x3)<<16)
1110#define DDR0_09_RTT_0_DECODE(n) ((((u32)(n))>>16)&0x3)
1111#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
1112#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1113#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F)
1114#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
1115#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1116#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((u32)(n))>>0)&0x7F)
1117
1118#define DDR0_10 0x0A
1119#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
1120#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
1121#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((u32)(n))>>16)&0x1)
1122#define DDR0_10_CS_MAP_MASK 0x00000300
1123#define DDR0_10_CS_MAP_NO_MEM 0x00000000
1124#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
1125#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
1126#define DDR0_10_CS_MAP_ENCODE(n) ((((u32)(n))&0x3)<<8)
1127#define DDR0_10_CS_MAP_DECODE(n) ((((u32)(n))>>8)&0x3)
1128#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
1129#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<0)
1130#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((u32)(n))>>0)&0x1F)
1131
1132#define DDR0_11 0x0B
1133#define DDR0_11_SREFRESH_MASK 0x01000000
1134#define DDR0_11_SREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<24)
1135#define DDR0_11_SREFRESH_DECODE(n) ((((u32)(n))>>24)&0x1F)
1136#define DDR0_11_TXSNR_MASK 0x00FF0000
1137#define DDR0_11_TXSNR_ENCODE(n) ((((u32)(n))&0xFF)<<16)
1138#define DDR0_11_TXSNR_DECODE(n) ((((u32)(n))>>16)&0xFF)
1139#define DDR0_11_TXSR_MASK 0x0000FF00
1140#define DDR0_11_TXSR_ENCODE(n) ((((u32)(n))&0xFF)<<8)
1141#define DDR0_11_TXSR_DECODE(n) ((((u32)(n))>>8)&0xFF)
1142
1143#define DDR0_12 0x0C
1144#define DDR0_12_TCKE_MASK 0x0000007
1145#define DDR0_12_TCKE_ENCODE(n) ((((u32)(n))&0x7)<<0)
1146#define DDR0_12_TCKE_DECODE(n) ((((u32)(n))>>0)&0x7)
1147
1148#define DDR0_14 0x0E
1149#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
1150#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((u32)(n))&0x1)<<24)
1151#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((u32)(n))>>24)&0x1)
1152#define DDR0_14_REDUC_MASK 0x00010000
1153#define DDR0_14_REDUC_64BITS 0x00000000
1154#define DDR0_14_REDUC_32BITS 0x00010000
1155#define DDR0_14_REDUC_ENCODE(n) ((((u32)(n))&0x1)<<16)
1156#define DDR0_14_REDUC_DECODE(n) ((((u32)(n))>>16)&0x1)
1157#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
1158#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((u32)(n))&0x1)<<8)
1159#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((u32)(n))>>8)&0x1)
1160
1161#define DDR0_17 0x11
1162#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
1163#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1164#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((u32)(n))>>24)&0x7F)
1165#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
1166#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
1167#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
1168#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
1169#define DDR0_17_DLLLOCKREG_DECODE(n) ((((u32)(n))>>16)&0x1)
1170#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
1171#define DDR0_17_DLL_LOCK_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1172#define DDR0_17_DLL_LOCK_DECODE(n) ((((u32)(n))>>8)&0x7F)
1173
1174#define DDR0_18 0x12
1175#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
1176#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
1177#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1178#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((u32)(n))>>24)&0x7F)
1179#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
1180#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1181#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((u32)(n))>>16)&0x7F)
1182#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
1183#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1184#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((u32)(n))>>8)&0x7F)
1185#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
1186#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1187#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((u32)(n))>>0)&0x7F)
1188
1189#define DDR0_19 0x13
1190#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
1191#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
1192#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1193#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((u32)(n))>>24)&0x7F)
1194#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
1195#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1196#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((u32)(n))>>16)&0x7F)
1197#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
1198#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1199#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((u32)(n))>>8)&0x7F)
1200#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
1201#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1202#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((u32)(n))>>0)&0x7F)
1203
1204#define DDR0_20 0x14
1205#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
1206#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1207#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((u32)(n))>>24)&0x7F)
1208#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
1209#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1210#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((u32)(n))>>16)&0x7F)
1211#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
1212#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1213#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((u32)(n))>>8)&0x7F)
1214#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
1215#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1216#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((u32)(n))>>0)&0x7F)
1217
1218#define DDR0_21 0x15
1219#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
1220#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1221#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((u32)(n))>>24)&0x7F)
1222#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
1223#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1224#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((u32)(n))>>16)&0x7F)
1225#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
1226#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1227#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((u32)(n))>>8)&0x7F)
1228#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
1229#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1230#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((u32)(n))>>0)&0x7F)
1231
1232#define DDR0_22 0x16
1233#define DDR0_22_CTRL_RAW_MASK 0x03000000
1234#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000
1235#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000
1236#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000
1237#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000
1238#define DDR0_22_CTRL_RAW_ENCODE(n) ((((u32)(n))&0x3)<<24)
1239#define DDR0_22_CTRL_RAW_DECODE(n) ((((u32)(n))>>24)&0x3)
1240#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
1241#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1242#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>16)&0x7F)
1243#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
1244#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1245#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((u32)(n))>>8)&0x7F)
1246#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
1247#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1248#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((u32)(n))>>0)&0x7F)
1249
1250#define DDR0_23 0x17
1251#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
1252#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<24)
1253#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((u32)(n))>>24)&0x3)
1254#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
1255#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<16)
1256#define DDR0_23_ECC_C_SYND_DECODE(n) ((((u32)(n))>>16)&0xFF)
1257#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
1258#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<8)
1259#define DDR0_23_ECC_U_SYND_DECODE(n) ((((u32)(n))>>8)&0xFF)
1260#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
1261#define DDR0_23_FWC_ENCODE(n) ((((u32)(n))&0x1)<<0)
1262#define DDR0_23_FWC_DECODE(n) ((((u32)(n))>>0)&0x1)
1263
1264#define DDR0_24 0x18
1265#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
1266#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((u32)(n))&0x3)<<24)
1267#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((u32)(n))>>24)&0x3)
1268#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
1269#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<16)
1270#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((u32)(n))>>16)&0x3)
1271#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
1272#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<8)
1273#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((u32)(n))>>8)&0x3)
1274#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
1275#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<0)
1276#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((u32)(n))>>0)&0x3)
1277
1278#define DDR0_25 0x19
1279#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
1280#define DDR0_25_VERSION_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
1281#define DDR0_25_VERSION_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
1282#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
1283#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((u32)(n))&0x3FF)<<0)
1284#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((u32)(n))>>0)&0x3FF)
1285
1286#define DDR0_26 0x1A
1287#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
1288#define DDR0_26_TRAS_MAX_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
1289#define DDR0_26_TRAS_MAX_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
1290#define DDR0_26_TREF_MASK 0x00003FFF
1291#define DDR0_26_TREF_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
1292#define DDR0_26_TREF_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
1293
1294#define DDR0_27 0x1B
1295#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
1296#define DDR0_27_EMRS_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
1297#define DDR0_27_EMRS_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
1298#define DDR0_27_TINIT_MASK 0x0000FFFF
1299#define DDR0_27_TINIT_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
1300#define DDR0_27_TINIT_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
1301
1302#define DDR0_28 0x1C
1303#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
1304#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
1305#define DDR0_28_EMRS3_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
1306#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
1307#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
1308#define DDR0_28_EMRS2_DATA_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
1309
1310#define DDR0_31 0x1F
1311#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
1312#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
1313#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
1314
1315#define DDR0_32 0x20
1316#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
1317#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1318#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1319
1320#define DDR0_33 0x21
1321#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
1322#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1323#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1324
1325#define DDR0_34 0x22
1326#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
1327#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1328#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1329
1330#define DDR0_35 0x23
1331#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
1332#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1333#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1334
1335#define DDR0_36 0x24
1336#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
1337#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1338#define DDR0_36_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1339
1340#define DDR0_37 0x25
1341#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
1342#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1343#define DDR0_37_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1344
1345#define DDR0_38 0x26
1346#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
1347#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1348#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1349
1350#define DDR0_39 0x27
1351#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
1352#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1353#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1354
1355#define DDR0_40 0x28
1356#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
1357#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1358#define DDR0_40_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1359
1360#define DDR0_41 0x29
1361#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
1362#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1363#define DDR0_41_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1364
1365#define DDR0_42 0x2A
1366#define DDR0_42_ADDR_PINS_MASK 0x07000000
1367#define DDR0_42_ADDR_PINS_ENCODE(n) ((((u32)(n))&0x7)<<24)
1368#define DDR0_42_ADDR_PINS_DECODE(n) ((((u32)(n))>>24)&0x7)
1369#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
1370#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((u32)(n))&0xF)<<0)
1371#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((u32)(n))>>0)&0xF)
1372
1373#define DDR0_43 0x2B
1374#define DDR0_43_TWR_MASK 0x07000000
1375#define DDR0_43_TWR_ENCODE(n) ((((u32)(n))&0x7)<<24)
1376#define DDR0_43_TWR_DECODE(n) ((((u32)(n))>>24)&0x7)
1377#define DDR0_43_APREBIT_MASK 0x000F0000
1378#define DDR0_43_APREBIT_ENCODE(n) ((((u32)(n))&0xF)<<16)
1379#define DDR0_43_APREBIT_DECODE(n) ((((u32)(n))>>16)&0xF)
1380#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
1381#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((u32)(n))&0x7)<<8)
1382#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((u32)(n))>>8)&0x7)
1383#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
1384#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
1385#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
1386#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((u32)(n))&0x1)<<0)
1387#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((u32)(n))>>0)&0x1)
1388
1389#define DDR0_44 0x2C
1390#define DDR0_44_TRCD_MASK 0x000000FF
1391#define DDR0_44_TRCD_ENCODE(n) ((((u32)(n))&0xFF)<<0)
1392#define DDR0_44_TRCD_DECODE(n) ((((u32)(n))>>0)&0xFF)
1393
1394#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
1395
Stefan Roese5ff88932008-09-08 14:11:12 +02001396#ifndef __ASSEMBLY__
Stefan Roese066003b2010-05-25 15:23:07 +02001397struct sdram_timing {
1398 u32 wrdtr;
1399 u32 clktr;
1400};
1401
Stefan Roese5ff88932008-09-08 14:11:12 +02001402/*
1403 * Prototypes
1404 */
Stefan Roese5ff88932008-09-08 14:11:12 +02001405inline void ppc4xx_ibm_ddr2_register_dump(void);
1406u32 mfdcr_any(u32);
1407void mtdcr_any(u32, u32);
1408u32 ddr_wrdtr(u32);
1409u32 ddr_clktr(u32);
1410void spd_ddr_init_hang(void);
1411u32 DQS_autocalibration(void);
Stefan Roesefb951692009-09-28 17:33:45 +02001412phys_size_t sdram_memsize(void);
1413void dcbz_area(u32 start_address, u32 num_bytes);
Stefan Roese5ff88932008-09-08 14:11:12 +02001414#endif /* __ASSEMBLY__ */
1415
Stefan Roese17ceb062008-06-02 14:59:21 +02001416#endif /* _PPC4xx_SDRAM_H_ */