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York Sun34e026f2014-03-27 17:54:47 -07001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * calculate the organization and timing parameter
5 * from ddr3 spd, please refer to the spec
6 * JEDEC standard No.21-C 4_01_02_12R23A.pdf
7 *
8 *
9 */
10
11#include <common.h>
12#include <fsl_ddr_sdram.h>
13
14#include <fsl_ddr.h>
15
16/*
17 * Calculate the Density of each Physical Rank.
18 * Returned size is in bytes.
19 *
20 * Total DIMM size =
21 * sdram capacity(bit) / 8 * primary bus width / sdram width
22 * * Logical Ranks per DIMM
23 *
24 * where: sdram capacity = spd byte4[3:0]
25 * primary bus width = spd byte13[2:0]
26 * sdram width = spd byte12[2:0]
27 * Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
28 * spd byte12{5:3] * spd byte6[6:4] for 3DS
29 *
30 * To simplify each rank size = total DIMM size / Number of Package Ranks
31 * where Number of Package Ranks = spd byte12[5:3]
32 *
33 * SPD byte4 - sdram density and banks
34 * bit[3:0] size(bit) size(byte)
35 * 0000 256Mb 32MB
36 * 0001 512Mb 64MB
37 * 0010 1Gb 128MB
38 * 0011 2Gb 256MB
39 * 0100 4Gb 512MB
40 * 0101 8Gb 1GB
41 * 0110 16Gb 2GB
42 * 0111 32Gb 4GB
43 *
44 * SPD byte13 - module memory bus width
45 * bit[2:0] primary bus width
46 * 000 8bits
47 * 001 16bits
48 * 010 32bits
49 * 011 64bits
50 *
51 * SPD byte12 - module organization
52 * bit[2:0] sdram device width
53 * 000 4bits
54 * 001 8bits
55 * 010 16bits
56 * 011 32bits
57 *
58 * SPD byte12 - module organization
59 * bit[5:3] number of package ranks per DIMM
60 * 000 1
61 * 001 2
62 * 010 3
63 * 011 4
64 *
65 * SPD byte6 - SDRAM package type
66 * bit[6:4] Die count
67 * 000 1
68 * 001 2
69 * 010 3
70 * 011 4
71 * 100 5
72 * 101 6
73 * 110 7
74 * 111 8
75 *
76 * SPD byte6 - SRAM package type
77 * bit[1:0] Signal loading
78 * 00 Not specified
79 * 01 Multi load stack
80 * 10 Sigle load stack (3DS)
81 * 11 Reserved
82 */
83static unsigned long long
84compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
85{
86 unsigned long long bsize;
87
88 int nbit_sdram_cap_bsize = 0;
89 int nbit_primary_bus_width = 0;
90 int nbit_sdram_width = 0;
91 int die_count = 0;
92 bool package_3ds;
93
94 if ((spd->density_banks & 0xf) <= 7)
95 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
96 if ((spd->bus_width & 0x7) < 4)
97 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
98 if ((spd->organization & 0x7) < 4)
99 nbit_sdram_width = (spd->organization & 0x7) + 2;
100 package_3ds = (spd->package_type & 0x3) == 0x2;
101 if (package_3ds)
102 die_count = (spd->package_type >> 4) & 0x7;
103
104 bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
105 nbit_primary_bus_width - nbit_sdram_width +
106 die_count);
107
108 debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
109
110 return bsize;
111}
112
113#define spd_to_ps(mtb, ftb) \
114 (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
115/*
York Sun1d71efb2014-08-01 15:51:00 -0700116 * ddr_compute_dimm_parameters for DDR4 SPD
York Sun34e026f2014-03-27 17:54:47 -0700117 *
118 * Compute DIMM parameters based upon the SPD information in spd.
119 * Writes the results to the dimm_params_t structure pointed by pdimm.
120 *
121 */
122unsigned int
123ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
124 dimm_params_t *pdimm,
125 unsigned int dimm_number)
126{
127 unsigned int retval;
128 int i;
129
130 if (spd->mem_type) {
131 if (spd->mem_type != SPD_MEMTYPE_DDR4) {
132 printf("DIMM %u: is not a DDR4 SPD.\n", dimm_number);
133 return 1;
134 }
135 } else {
136 memset(pdimm, 0, sizeof(dimm_params_t));
137 return 1;
138 }
139
140 retval = ddr4_spd_check(spd);
141 if (retval) {
142 printf("DIMM %u: failed checksum\n", dimm_number);
143 return 2;
144 }
145
146 /*
147 * The part name in ASCII in the SPD EEPROM is not null terminated.
148 * Guarantee null termination here by presetting all bytes to 0
149 * and copying the part name in ASCII from the SPD onto it
150 */
151 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
152 if ((spd->info_size_crc & 0xF) > 2)
153 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
154
155 /* DIMM organization parameters */
156 pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
157 pdimm->rank_density = compute_ranksize(spd);
158 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
159 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
160 if ((spd->bus_width >> 3) & 0x3)
161 pdimm->ec_sdram_width = 8;
162 else
163 pdimm->ec_sdram_width = 0;
164 pdimm->data_width = pdimm->primary_sdram_width
165 + pdimm->ec_sdram_width;
166 pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
167
York Sun1d71efb2014-08-01 15:51:00 -0700168 /* These are the types defined by the JEDEC SPD spec */
York Sun34e026f2014-03-27 17:54:47 -0700169 pdimm->mirrored_dimm = 0;
170 pdimm->registered_dimm = 0;
York Sun1d71efb2014-08-01 15:51:00 -0700171 switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
172 case DDR4_SPD_MODULETYPE_RDIMM:
York Sun34e026f2014-03-27 17:54:47 -0700173 /* Registered/buffered DIMMs */
174 pdimm->registered_dimm = 1;
175 break;
176
York Sun1d71efb2014-08-01 15:51:00 -0700177 case DDR4_SPD_MODULETYPE_UDIMM:
178 case DDR4_SPD_MODULETYPE_SO_DIMM:
York Sun34e026f2014-03-27 17:54:47 -0700179 /* Unbuffered DIMMs */
180 if (spd->mod_section.unbuffered.addr_mapping & 0x1)
181 pdimm->mirrored_dimm = 1;
182 break;
183
184 default:
185 printf("unknown module_type 0x%02X\n", spd->module_type);
186 return 1;
187 }
188
189 /* SDRAM device parameters */
190 pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
191 pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
192 pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
193 pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
194
195 /*
196 * The SPD spec has not the ECC bit,
197 * We consider the DIMM as ECC capability
198 * when the extension bus exist
199 */
200 if (pdimm->ec_sdram_width)
201 pdimm->edc_config = 0x02;
202 else
203 pdimm->edc_config = 0x00;
204
205 /*
206 * The SPD spec has not the burst length byte
207 * but DDR4 spec has nature BL8 and BC4,
208 * BL8 -bit3, BC4 -bit2
209 */
210 pdimm->burst_lengths_bitmask = 0x0c;
211 pdimm->row_density = __ilog2(pdimm->rank_density);
212
213 /* MTB - medium timebase
214 * The MTB in the SPD spec is 125ps,
215 *
216 * FTB - fine timebase
217 * use 1/10th of ps as our unit to avoid floating point
218 * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
219 */
220 if ((spd->timebases & 0xf) == 0x0) {
221 pdimm->mtb_ps = 125;
222 pdimm->ftb_10th_ps = 10;
223
224 } else {
225 printf("Unknown Timebases\n");
226 }
227
228 /* sdram minimum cycle time */
229 pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
230
231 /* sdram max cycle time */
232 pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
233
234 /*
235 * CAS latency supported
236 * bit0 - CL7
237 * bit4 - CL11
238 * bit8 - CL15
239 * bit12- CL19
240 * bit16- CL23
241 */
242 pdimm->caslat_x = (spd->caslat_b1 << 7) |
243 (spd->caslat_b2 << 15) |
244 (spd->caslat_b3 << 23);
245
246 BUG_ON(spd->caslat_b4 != 0);
247
248 /*
249 * min CAS latency time
250 */
251 pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
252
253 /*
254 * min RAS to CAS delay time
255 */
256 pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
257
258 /*
259 * Min Row Precharge Delay Time
260 */
261 pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
262
263 /* min active to precharge delay time */
264 pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
265 spd->tras_min_lsb) * pdimm->mtb_ps;
266
267 /* min active to actice/refresh delay time */
268 pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
269 spd->trc_min_lsb), spd->fine_trc_min);
270 /* Min Refresh Recovery Delay Time */
271 pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
272 pdimm->mtb_ps;
273 pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
274 pdimm->mtb_ps;
275 pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
276 pdimm->mtb_ps;
277 /* min four active window delay time */
278 pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
279 pdimm->mtb_ps;
280
281 /* min row active to row active delay time, different bank group */
282 pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
283 /* min row active to row active delay time, same bank group */
284 pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
285 /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
286 pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
287
288 /*
289 * Average periodic refresh interval
290 * tREFI = 7.8 us at normal temperature range
291 */
292 pdimm->refresh_rate_ps = 7800000;
293
294 for (i = 0; i < 18; i++)
295 pdimm->dq_mapping[i] = spd->mapping[i];
296
297 pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
298
299 return 0;
300}