wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
| 4 | * |
| 5 | * (C) Copyright 2002 |
| 6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 7 | * Marius Groeger <mgroeger@sysgo.de> |
| 8 | * |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 9 | * (C) Copyright 2002 |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 10 | * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de> |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 11 | * |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 12 | * (C) Copyright 2003 (2 x 16 bit Flash bank patches) |
| 13 | * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de> |
| 14 | * |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 15 | * See file CREDITS for list of people who contributed to this |
| 16 | * project. |
| 17 | * |
| 18 | * This program is free software; you can redistribute it and/or |
| 19 | * modify it under the terms of the GNU General Public License as |
| 20 | * published by the Free Software Foundation; either version 2 of |
| 21 | * the License, or (at your option) any later version. |
| 22 | * |
| 23 | * This program is distributed in the hope that it will be useful, |
| 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 26 | * GNU General Public License for more details. |
| 27 | * |
| 28 | * You should have received a copy of the GNU General Public License |
| 29 | * along with this program; if not, write to the Free Software |
| 30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 31 | * MA 02111-1307 USA |
| 32 | */ |
| 33 | |
| 34 | #include <common.h> |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 35 | #include <asm/arch/pxa-regs.h> |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 36 | |
| 37 | #define FLASH_BANK_SIZE 0x02000000 |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 38 | #define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */ |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 39 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 40 | flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 41 | |
| 42 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 43 | /** |
| 44 | * flash_init: - initialize data structures for flash chips |
| 45 | * |
| 46 | * @return: size of the flash |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 47 | */ |
| 48 | |
| 49 | ulong flash_init(void) |
| 50 | { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 51 | int i, j; |
| 52 | ulong size = 0; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 53 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 54 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 55 | ulong flashbase = 0; |
| 56 | flash_info[i].flash_id = |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 57 | (INTEL_MANUFACT & FLASH_VENDMASK) | |
| 58 | (INTEL_ID_28F128J3 & FLASH_TYPEMASK); |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 59 | flash_info[i].size = FLASH_BANK_SIZE; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 60 | flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; |
| 61 | memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 62 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 63 | switch (i) { |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 64 | case 0: |
| 65 | flashbase = PHYS_FLASH_1; |
| 66 | break; |
| 67 | default: |
| 68 | panic("configured too many flash banks!\n"); |
| 69 | break; |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 70 | } |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 71 | for (j = 0; j < flash_info[i].sector_count; j++) { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 72 | flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; |
| 73 | } |
| 74 | size += flash_info[i].size; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 75 | } |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 76 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 77 | /* Protect monitor and environment sectors */ |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 78 | flash_protect(FLAG_PROTECT_SET, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | CONFIG_SYS_FLASH_BASE, |
| 80 | CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 81 | &flash_info[0]); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 82 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 83 | flash_protect(FLAG_PROTECT_SET, |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 84 | CONFIG_ENV_ADDR, |
| 85 | CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 86 | &flash_info[0]); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 87 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 88 | return size; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 89 | } |
| 90 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 91 | |
| 92 | /** |
| 93 | * flash_print_info: - print information about the flash situation |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 94 | */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 95 | |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 96 | void flash_print_info (flash_info_t *info) |
| 97 | { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 98 | int i, j; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 99 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) { |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 101 | |
| 102 | switch (info->flash_id & FLASH_VENDMASK) { |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 103 | case (INTEL_MANUFACT & FLASH_VENDMASK): |
| 104 | printf ("Intel: "); |
| 105 | break; |
| 106 | default: |
| 107 | printf ("Unknown Vendor "); |
| 108 | break; |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 109 | } |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 110 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 111 | switch (info->flash_id & FLASH_TYPEMASK) { |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 112 | case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): |
| 113 | printf("28F128J3 (128Mbit)\n"); |
| 114 | break; |
| 115 | default: |
| 116 | printf("Unknown Chip Type\n"); |
| 117 | return; |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 118 | } |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 119 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 120 | printf(" Size: %ld MB in %d Sectors\n", |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 121 | info->size >> 20, info->sector_count); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 122 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 123 | printf(" Sector Start Addresses:"); |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 124 | for (i = 0; i < info->sector_count; i++) { |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 125 | if ((i % 5) == 0) printf ("\n "); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 126 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 127 | printf (" %08lX%s", info->start[i], |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 128 | info->protect[i] ? " (RO)" : " "); |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 129 | } |
| 130 | printf ("\n"); |
| 131 | info++; |
| 132 | } |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 133 | } |
| 134 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 135 | |
| 136 | /** |
| 137 | * flash_erase: - erase flash sectors |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 138 | */ |
| 139 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 140 | int flash_erase(flash_info_t *info, int s_first, int s_last) |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 141 | { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 142 | int flag, prot, sect; |
| 143 | int rc = ERR_OK; |
Graeme Russ | a60d1e5 | 2011-07-15 23:31:37 +0000 | [diff] [blame] | 144 | ulong start; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 145 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 146 | if (info->flash_id == FLASH_UNKNOWN) |
| 147 | return ERR_UNKNOWN_FLASH_TYPE; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 148 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 149 | if ((s_first < 0) || (s_first > s_last)) { |
| 150 | return ERR_INVAL; |
| 151 | } |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 152 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 153 | if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 154 | return ERR_UNKNOWN_FLASH_VENDOR; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 155 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 156 | prot = 0; |
| 157 | for (sect=s_first; sect<=s_last; ++sect) { |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 158 | if (info->protect[sect]) prot++; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 159 | } |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 160 | |
| 161 | if (prot) return ERR_PROTECTED; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 162 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 163 | /* |
| 164 | * Disable interrupts which might cause a timeout |
| 165 | * here. Remember that our exception vectors are |
| 166 | * at address 0 in the flash, and we don't want a |
| 167 | * (ticker) exception to happen while the flash |
| 168 | * chip is in programming mode. |
| 169 | */ |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 170 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 171 | flag = disable_interrupts(); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 172 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 173 | /* Start erase on unprotected sectors */ |
| 174 | for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 175 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 176 | printf("Erasing sector %2d ... ", sect); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 177 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 178 | /* arm simple, non interrupt dependent timer */ |
Graeme Russ | a60d1e5 | 2011-07-15 23:31:37 +0000 | [diff] [blame] | 179 | start = get_timer(0); |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 180 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 181 | if (info->protect[sect] == 0) { /* not protected */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 182 | u32 * volatile addr = (u32 * volatile)(info->start[sect]); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 183 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 184 | /* erase sector: */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 185 | /* The strata flashs are aligned side by side on */ |
| 186 | /* the data bus, so we have to write the commands */ |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 187 | /* to both chips here: */ |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 188 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 189 | *addr = 0x00200020; /* erase setup */ |
| 190 | *addr = 0x00D000D0; /* erase confirm */ |
| 191 | |
| 192 | while ((*addr & 0x00800080) != 0x00800080) { |
Graeme Russ | a60d1e5 | 2011-07-15 23:31:37 +0000 | [diff] [blame] | 193 | if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 194 | *addr = 0x00B000B0; /* suspend erase*/ |
| 195 | *addr = 0x00FF00FF; /* read mode */ |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 196 | rc = ERR_TIMOUT; |
| 197 | goto outahere; |
| 198 | } |
| 199 | } |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 200 | *addr = 0x00500050; /* clear status register cmd. */ |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 201 | *addr = 0x00FF00FF; /* reset to read mode */ |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 202 | } |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 203 | printf("ok.\n"); |
| 204 | } |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 205 | if (ctrlc()) printf("User Interrupt!\n"); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 206 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 207 | outahere: |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 208 | /* allow flash to settle - wait 10 ms */ |
| 209 | udelay_masked(10000); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 210 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 211 | if (flag) enable_interrupts(); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 212 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 213 | return rc; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 214 | } |
| 215 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 216 | /** |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 217 | * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 218 | */ |
| 219 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 220 | static int write_long (flash_info_t *info, ulong dest, ulong data) |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 221 | { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 222 | u32 * volatile addr = (u32 * volatile)dest, val; |
| 223 | int rc = ERR_OK; |
| 224 | int flag; |
Graeme Russ | a60d1e5 | 2011-07-15 23:31:37 +0000 | [diff] [blame] | 225 | ulong start; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 226 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 227 | /* read array command - just for the case... */ |
| 228 | *addr = 0x00FF00FF; |
| 229 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 230 | /* Check if Flash is (sufficiently) erased */ |
| 231 | if ((*addr & data) != data) return ERR_NOT_ERASED; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 232 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 233 | /* |
| 234 | * Disable interrupts which might cause a timeout |
| 235 | * here. Remember that our exception vectors are |
| 236 | * at address 0 in the flash, and we don't want a |
| 237 | * (ticker) exception to happen while the flash |
| 238 | * chip is in programming mode. |
| 239 | */ |
| 240 | flag = disable_interrupts(); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 241 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 242 | /* clear status register command */ |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 243 | *addr = 0x00500050; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 244 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 245 | /* program set-up command */ |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 246 | *addr = 0x00400040; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 247 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 248 | /* latch address/data */ |
| 249 | *addr = data; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 250 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 251 | /* arm simple, non interrupt dependent timer */ |
Graeme Russ | a60d1e5 | 2011-07-15 23:31:37 +0000 | [diff] [blame] | 252 | start = get_timer(0); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 253 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 254 | /* wait while polling the status register */ |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 255 | while(((val = *addr) & 0x00800080) != 0x00800080) { |
Graeme Russ | a60d1e5 | 2011-07-15 23:31:37 +0000 | [diff] [blame] | 256 | if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 257 | rc = ERR_TIMOUT; |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 258 | /* suspend program command */ |
| 259 | *addr = 0x00B000B0; |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 260 | goto outahere; |
| 261 | } |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 262 | } |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 263 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 264 | /* check for errors */ |
| 265 | if(val & 0x001A001A) { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 266 | printf("\nFlash write error %02x at address %08lx\n", |
| 267 | (int)val, (unsigned long)dest); |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 268 | if(val & 0x00080008) { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 269 | printf("Voltage range error.\n"); |
| 270 | rc = ERR_PROG_ERROR; |
| 271 | goto outahere; |
| 272 | } |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 273 | if(val & 0x00020002) { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 274 | printf("Device protect error.\n"); |
| 275 | rc = ERR_PROTECTED; |
| 276 | goto outahere; |
| 277 | } |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 278 | if(val & 0x00100010) { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 279 | printf("Programming error.\n"); |
| 280 | rc = ERR_PROG_ERROR; |
| 281 | goto outahere; |
| 282 | } |
| 283 | rc = ERR_PROG_ERROR; |
| 284 | goto outahere; |
| 285 | } |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 286 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 287 | outahere: |
| 288 | /* read array command */ |
| 289 | *addr = 0x00FF00FF; |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 290 | if (flag) enable_interrupts(); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 291 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 292 | return rc; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 293 | } |
| 294 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 295 | |
| 296 | /** |
| 297 | * write_buf: - Copy memory to flash. |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 298 | * |
| 299 | * @param info: |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 300 | * @param src: source of copy transaction |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 301 | * @param addr: where to copy to |
| 302 | * @param cnt: number of bytes to copy |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 303 | * |
| 304 | * @return error code |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 305 | */ |
| 306 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 307 | /* "long" version, uses 32bit words */ |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 308 | int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
| 309 | { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 310 | ulong cp, wp; |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 311 | ulong data; |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 312 | int l; |
| 313 | int i, rc; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 314 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 315 | wp = (addr & ~3); /* get lower word aligned address */ |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 316 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 317 | /* |
| 318 | * handle unaligned start bytes |
| 319 | */ |
| 320 | if ((l = addr - wp) != 0) { |
| 321 | data = 0; |
| 322 | for (i=0, cp=wp; i<l; ++i, ++cp) { |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 323 | data = (data >> 8) | (*(uchar *)cp << 24); |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 324 | } |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 325 | for (; i<4 && cnt>0; ++i) { |
| 326 | data = (data >> 8) | (*src++ << 24); |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 327 | --cnt; |
| 328 | ++cp; |
| 329 | } |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 330 | for (; cnt==0 && i<4; ++i, ++cp) { |
| 331 | data = (data >> 8) | (*(uchar *)cp << 24); |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 332 | } |
| 333 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 334 | if ((rc = write_long(info, wp, data)) != 0) { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 335 | return (rc); |
| 336 | } |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 337 | wp += 4; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 338 | } |
| 339 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 340 | /* |
| 341 | * handle word aligned part |
| 342 | */ |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 343 | while (cnt >= 4) { |
| 344 | data = *((ulong*)src); |
| 345 | if ((rc = write_long(info, wp, data)) != 0) { |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 346 | return (rc); |
| 347 | } |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 348 | src += 4; |
| 349 | wp += 4; |
| 350 | cnt -= 4; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 351 | } |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 352 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 353 | if (cnt == 0) return ERR_OK; |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 354 | |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 355 | /* |
| 356 | * handle unaligned tail bytes |
| 357 | */ |
| 358 | data = 0; |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 359 | for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
| 360 | data = (data >> 8) | (*src++ << 24); |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 361 | --cnt; |
| 362 | } |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 363 | for (; i<4; ++i, ++cp) { |
| 364 | data = (data >> 8) | (*(uchar *)cp << 24); |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 365 | } |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 366 | |
wdenk | b98fff1 | 2004-02-09 20:51:26 +0000 | [diff] [blame] | 367 | return write_long(info, wp, data); |
wdenk | f9087a3 | 2002-11-03 00:30:25 +0000 | [diff] [blame] | 368 | } |